1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a57.h> 10#include <cpu_macros.S> 11#include <debug.h> 12 13 /* --------------------------------------------- 14 * Disable intra-cluster coherency 15 * Clobbers: r0-r1 16 * --------------------------------------------- 17 */ 18func cortex_a57_disable_smp 19 ldcopr16 r0, r1, CPUECTLR 20 bic64_imm r0, r1, CPUECTLR_SMP_BIT 21 stcopr16 r0, r1, CPUECTLR 22 bx lr 23endfunc cortex_a57_disable_smp 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * Clobbers: r0-r2 28 * --------------------------------------------- 29 */ 30func cortex_a57_disable_l2_prefetch 31 ldcopr16 r0, r1, CPUECTLR 32 orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 33 bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ 34 CPUECTLR_L2_DPFTCH_DIST_MASK) 35 stcopr16 r0, r1, CPUECTLR 36 isb 37 dsb ish 38 bx lr 39endfunc cortex_a57_disable_l2_prefetch 40 41 /* --------------------------------------------- 42 * Disable debug interfaces 43 * --------------------------------------------- 44 */ 45func cortex_a57_disable_ext_debug 46 mov r0, #1 47 stcopr r0, DBGOSDLR 48 isb 49 dsb sy 50 bx lr 51endfunc cortex_a57_disable_ext_debug 52 53 /* ------------------------------------------------- 54 * The CPU Ops reset function for Cortex-A57. 55 * ------------------------------------------------- 56 */ 57func cortex_a57_reset_func 58 /* --------------------------------------------- 59 * Enable the SMP bit. 60 * --------------------------------------------- 61 */ 62 ldcopr16 r0, r1, CPUECTLR 63 orr64_imm r0, r1, CPUECTLR_SMP_BIT 64 stcopr16 r0, r1, CPUECTLR 65 isb 66 bx lr 67endfunc cortex_a57_reset_func 68 69 /* ---------------------------------------------------- 70 * The CPU Ops core power down function for Cortex-A57. 71 * ---------------------------------------------------- 72 */ 73func cortex_a57_core_pwr_dwn 74 push {r12, lr} 75 76 /* Assert if cache is enabled */ 77#if ASM_ASSERTION 78 ldcopr r0, SCTLR 79 tst r0, #SCTLR_C_BIT 80 ASM_ASSERT(eq) 81#endif 82 83 /* --------------------------------------------- 84 * Disable the L2 prefetches. 85 * --------------------------------------------- 86 */ 87 bl cortex_a57_disable_l2_prefetch 88 89 /* --------------------------------------------- 90 * Flush L1 caches. 91 * --------------------------------------------- 92 */ 93 mov r0, #DC_OP_CISW 94 bl dcsw_op_level1 95 96 /* --------------------------------------------- 97 * Come out of intra cluster coherency 98 * --------------------------------------------- 99 */ 100 bl cortex_a57_disable_smp 101 102 /* --------------------------------------------- 103 * Force the debug interfaces to be quiescent 104 * --------------------------------------------- 105 */ 106 pop {r12, lr} 107 b cortex_a57_disable_ext_debug 108endfunc cortex_a57_core_pwr_dwn 109 110 /* ------------------------------------------------------- 111 * The CPU Ops cluster power down function for Cortex-A57. 112 * Clobbers: r0-r3 113 * ------------------------------------------------------- 114 */ 115func cortex_a57_cluster_pwr_dwn 116 push {r12, lr} 117 118 /* Assert if cache is enabled */ 119#if ASM_ASSERTION 120 ldcopr r0, SCTLR 121 tst r0, #SCTLR_C_BIT 122 ASM_ASSERT(eq) 123#endif 124 125 /* --------------------------------------------- 126 * Disable the L2 prefetches. 127 * --------------------------------------------- 128 */ 129 bl cortex_a57_disable_l2_prefetch 130 131 /* --------------------------------------------- 132 * Flush L1 caches. 133 * --------------------------------------------- 134 */ 135 mov r0, #DC_OP_CISW 136 bl dcsw_op_level1 137 138 /* --------------------------------------------- 139 * Disable the optional ACP. 140 * --------------------------------------------- 141 */ 142 bl plat_disable_acp 143 144 /* --------------------------------------------- 145 * Flush L2 caches. 146 * --------------------------------------------- 147 */ 148 mov r0, #DC_OP_CISW 149 bl dcsw_op_level2 150 151 /* --------------------------------------------- 152 * Come out of intra cluster coherency 153 * --------------------------------------------- 154 */ 155 bl cortex_a57_disable_smp 156 157 /* --------------------------------------------- 158 * Force the debug interfaces to be quiescent 159 * --------------------------------------------- 160 */ 161 pop {r12, lr} 162 b cortex_a57_disable_ext_debug 163endfunc cortex_a57_cluster_pwr_dwn 164 165declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 166 cortex_a57_reset_func, \ 167 cortex_a57_core_pwr_dwn, \ 168 cortex_a57_cluster_pwr_dwn 169