1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <delay_timer.h> 13 #include <dw_ufs.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <gicv2.h> 17 #include <hi3660.h> 18 #include <interrupt_props.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 41 /* Data structure which holds the extents of the trusted RAM for BL1 */ 42 static meminfo_t bl1_tzram_layout; 43 44 /****************************************************************************** 45 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 46 * interrupts. 47 *****************************************************************************/ 48 static const interrupt_prop_t g0_interrupt_props[] = { 49 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 50 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 51 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 52 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 53 }; 54 55 const gicv2_driver_data_t hikey960_gic_data = { 56 .gicd_base = GICD_REG_BASE, 57 .gicc_base = GICC_REG_BASE, 58 .interrupt_props = g0_interrupt_props, 59 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 60 }; 61 62 meminfo_t *bl1_plat_sec_mem_layout(void) 63 { 64 return &bl1_tzram_layout; 65 } 66 67 /* 68 * Perform any BL1 specific platform actions. 69 */ 70 void bl1_early_platform_setup(void) 71 { 72 unsigned int id, uart_base; 73 74 generic_delay_timer_init(); 75 hikey960_read_boardid(&id); 76 if (id == 5300) 77 uart_base = PL011_UART5_BASE; 78 else 79 uart_base = PL011_UART6_BASE; 80 /* Initialize the console to provide early debug support */ 81 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 82 83 /* Allow BL1 to see the whole Trusted RAM */ 84 bl1_tzram_layout.total_base = BL1_RW_BASE; 85 bl1_tzram_layout.total_size = BL1_RW_SIZE; 86 87 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 88 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 89 } 90 91 /* 92 * Perform the very early platform specific architecture setup here. At the 93 * moment this only does basic initialization. Later architectural setup 94 * (bl1_arch_setup()) does not do anything platform specific. 95 */ 96 void bl1_plat_arch_setup(void) 97 { 98 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 99 bl1_tzram_layout.total_size, 100 BL1_RO_BASE, 101 BL1_RO_LIMIT, 102 BL_COHERENT_RAM_BASE, 103 BL_COHERENT_RAM_END); 104 } 105 106 static void hikey960_ufs_reset(void) 107 { 108 unsigned int data, mask; 109 110 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 111 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 112 do { 113 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 114 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 115 /* use abb clk */ 116 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 117 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 118 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 119 mdelay(1); 120 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 121 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 122 123 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 124 do { 125 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 126 } while ((data & PERI_UFS_BIT) == 0); 127 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 128 mdelay(1); 129 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 130 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 131 MASK_UFS_DEVICE_RESET); 132 /* clear SC_DIV_UFS_PERIBUS */ 133 mask = SC_DIV_UFS_PERIBUS << 16; 134 mmio_write_32(CRG_CLKDIV17_REG, mask); 135 /* set SC_DIV_UFSPHY_CFG(3) */ 136 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 137 data = SC_DIV_UFSPHY_CFG(3); 138 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 139 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 140 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 141 data |= 0x39; 142 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 143 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 144 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 145 MASK_UFS_CLK_GATE_BYPASS); 146 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 147 148 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 149 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 150 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 151 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 152 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 153 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 154 mdelay(1); 155 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 156 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 157 mdelay(20); 158 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 159 0x03300330); 160 161 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 162 do { 163 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 164 } while (data & PERI_UFS_BIT); 165 } 166 167 static void hikey960_ufs_init(void) 168 { 169 dw_ufs_params_t ufs_params; 170 171 memset(&ufs_params, 0, sizeof(ufs_params)); 172 ufs_params.reg_base = UFS_REG_BASE; 173 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 174 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 175 176 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 177 hikey960_ufs_reset(); 178 dw_ufs_init(&ufs_params); 179 } 180 181 /* 182 * Function which will perform any remaining platform-specific setup that can 183 * occur after the MMU and data cache have been enabled. 184 */ 185 void bl1_platform_setup(void) 186 { 187 hikey960_clk_init(); 188 hikey960_pmu_init(); 189 hikey960_regulator_enable(); 190 hikey960_tzc_init(); 191 hikey960_peri_init(); 192 hikey960_ufs_init(); 193 hikey960_pinmux_init(); 194 hikey960_gpio_init(); 195 hikey960_io_setup(); 196 } 197 198 /* 199 * The following function checks if Firmware update is needed, 200 * by checking if TOC in FIP image is valid or not. 201 */ 202 unsigned int bl1_plat_get_next_image_id(void) 203 { 204 unsigned int mode, ret; 205 206 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 207 switch (mode & BOOT_MODE_MASK) { 208 case BOOT_MODE_RECOVERY: 209 ret = NS_BL1U_IMAGE_ID; 210 break; 211 default: 212 WARN("Invalid boot mode is found:%d\n", mode); 213 panic(); 214 } 215 return ret; 216 } 217 218 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 219 { 220 unsigned int index = 0; 221 222 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 223 if (bl1_tbbr_image_descs[index].image_id == image_id) 224 return &bl1_tbbr_image_descs[index]; 225 index++; 226 } 227 228 return NULL; 229 } 230 231 void bl1_plat_set_ep_info(unsigned int image_id, 232 entry_point_info_t *ep_info) 233 { 234 unsigned int data = 0; 235 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 236 237 if (image_id != NS_BL1U_IMAGE_ID) 238 panic(); 239 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 240 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 241 NS_BL1U_SIZE); 242 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 243 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 244 /* Initialize the GIC driver, cpu and distributor interfaces */ 245 gicv2_driver_init(&hikey960_gic_data); 246 gicv2_distif_init(); 247 gicv2_pcpu_distif_init(); 248 gicv2_cpuif_enable(); 249 /* CNTFRQ is read-only in EL1 */ 250 write_cntfrq_el0(plat_get_syscnt_freq2()); 251 data = read_cpacr_el1(); 252 do { 253 data |= 3 << 20; 254 write_cpacr_el1(data); 255 data = read_cpacr_el1(); 256 } while ((data & (3 << 20)) != (3 << 20)); 257 INFO("cpacr_el1:0x%x\n", data); 258 259 ep_info->args.arg0 = 0xffff & read_mpidr(); 260 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 261 DISABLE_ALL_EXCEPTIONS); 262 } 263