1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <console.h> 10 #include <coreboot.h> 11 #include <debug.h> 12 #include <generic_delay_timer.h> 13 #include <mmio.h> 14 #include <plat_private.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <uart_16550.h> 18 19 /* 20 * The next 2 constants identify the extents of the code & RO data region. 21 * These addresses are used by the MMU setup code and therefore they must be 22 * page-aligned. It is the responsibility of the linker script to ensure that 23 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 24 */ 25 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); 26 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); 27 28 static entry_point_info_t bl32_ep_info; 29 static entry_point_info_t bl33_ep_info; 30 31 /******************************************************************************* 32 * Return a pointer to the 'entry_point_info' structure of the next image for 33 * the security state specified. BL33 corresponds to the non-secure image type 34 * while BL32 corresponds to the secure image type. A NULL pointer is returned 35 * if the image does not exist. 36 ******************************************************************************/ 37 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 38 { 39 entry_point_info_t *next_image_info; 40 41 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 42 43 /* None of the images on this platform can have 0x0 as the entrypoint */ 44 if (next_image_info->pc) 45 return next_image_info; 46 else 47 return NULL; 48 } 49 50 #pragma weak params_early_setup 51 void params_early_setup(void *plat_param_from_bl2) 52 { 53 } 54 55 /******************************************************************************* 56 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 57 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 58 * are lost (potentially). This needs to be done before the MMU is initialized 59 * so that the memory layout can be used while creating page tables. 60 * BL2 has flushed this information to memory, so we are guaranteed to pick up 61 * good data. 62 ******************************************************************************/ 63 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 64 u_register_t arg2, u_register_t arg3) 65 { 66 static console_16550_t console; 67 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0; 68 void *plat_params_from_bl2 = (void *) arg1; 69 70 params_early_setup(plat_params_from_bl2); 71 72 #if COREBOOT 73 if (coreboot_serial.type) 74 console_16550_register(coreboot_serial.baseaddr, 75 coreboot_serial.input_hertz, 76 coreboot_serial.baud, 77 &console); 78 #else 79 console_16550_register(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 80 PLAT_RK_UART_BAUDRATE, &console); 81 #endif 82 83 VERBOSE("bl31_setup\n"); 84 85 /* Passing a NULL context is a critical programming error */ 86 assert(arg_from_bl2); 87 88 assert(arg_from_bl2->h.type == PARAM_BL31); 89 assert(arg_from_bl2->h.version >= VERSION_1); 90 91 bl32_ep_info = *arg_from_bl2->bl32_ep_info; 92 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 93 } 94 95 /******************************************************************************* 96 * Perform any BL3-1 platform setup code 97 ******************************************************************************/ 98 void bl31_platform_setup(void) 99 { 100 generic_delay_timer_init(); 101 plat_rockchip_soc_init(); 102 103 /* Initialize the gic cpu and distributor interfaces */ 104 plat_rockchip_gic_driver_init(); 105 plat_rockchip_gic_init(); 106 plat_rockchip_pmu_init(); 107 } 108 109 /******************************************************************************* 110 * Perform the very early platform specific architectural setup here. At the 111 * moment this is only intializes the mmu in a quick and dirty way. 112 ******************************************************************************/ 113 void bl31_plat_arch_setup(void) 114 { 115 plat_cci_init(); 116 plat_cci_enable(); 117 plat_configure_mmu_el3(BL31_RO_BASE, 118 BL_COHERENT_RAM_END - BL31_RO_BASE, 119 BL31_RO_BASE, 120 BL31_RO_LIMIT, 121 BL_COHERENT_RAM_BASE, 122 BL_COHERENT_RAM_END); 123 } 124