1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <gic_common.h> 13 #include <interrupt_props.h> 14 #include <tbbr/tbbr_img_def.h> 15 #include <utils_def.h> 16 #include "hi3798cv200.h" 17 #include "poplar_layout.h" /* BL memory region sizes, etc */ 18 19 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 20 #define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 21 22 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 23 #define PLATFORM_LINKER_ARCH aarch64 24 25 #define POPLAR_CRASH_UART_BASE PL011_UART0_BASE 26 #define POPLAR_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ 27 #define POPLAR_CONSOLE_BAUDRATE PL011_BAUDRATE 28 29 /* Generic platform constants */ 30 #define PLATFORM_STACK_SIZE (0x800) 31 32 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 33 #define BOOT_EMMC_NAME "l-loader.bin" 34 35 #define PLATFORM_CACHE_LINE_SIZE (64) 36 #define PLATFORM_CLUSTER_COUNT (1) 37 #define PLATFORM_CORE_COUNT (4) 38 #define PLATFORM_MAX_CPUS_PER_CLUSTER (4) 39 40 /* IO framework user */ 41 #define MAX_IO_DEVICES (4) 42 #define MAX_IO_HANDLES (4) 43 #define MAX_IO_BLOCK_DEVICES (2) 44 45 /* Memory size options */ 46 #define POPLAR_DRAM_SIZE_1G 0 47 #define POPLAR_DRAM_SIZE_2G 1 48 49 /* Memory map related constants */ 50 #define DDR_BASE (0x00000000) 51 52 #if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G) 53 #define DDR_SIZE (0x80000000) 54 #elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G) 55 #define DDR_SIZE (0x40000000) 56 #else 57 #error "Currently unsupported POPLAR_DRAM_SIZE_ID value" 58 #endif 59 60 #define DEVICE_BASE (0xF0000000) 61 #define DEVICE_SIZE (0x0F000000) 62 63 #define TEE_SEC_MEM_BASE (0x70000000) 64 #define TEE_SEC_MEM_SIZE (0x10000000) 65 66 /* Memory location options for TSP */ 67 #define POPLAR_SRAM_ID 0 68 #define POPLAR_DRAM_ID 1 69 70 /* 71 * DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several 72 * regions: 73 * - Secure DDR (default is the top 16MB) used by OP-TEE 74 * - Non-secure DDR (4MB) reserved for OP-TEE's future use 75 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 76 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 77 */ 78 #define DDR_SEC_SIZE 0x01000000 79 #define DDR_SEC_BASE 0x03000000 80 81 /* 82 * BL3-2 specific defines. 83 */ 84 85 /* 86 * The TSP currently executes from TZC secured area of DRAM. 87 */ 88 #define BL32_DRAM_BASE 0x03000000 89 #define BL32_DRAM_LIMIT 0x04000000 90 91 #ifdef SPD_opteed 92 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 93 #define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 94 #define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */ 95 #endif 96 97 #if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID) 98 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 99 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 100 #define BL32_BASE BL32_DRAM_BASE 101 #define BL32_LIMIT BL32_DRAM_LIMIT 102 #elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID) 103 #error "SRAM storage of TSP payload is currently unsupported" 104 #else 105 #error "Currently unsupported POPLAR_TSP_LOCATION_ID value" 106 #endif 107 108 /* BL32 is mandatory in AArch32 */ 109 #ifndef AARCH32 110 #ifdef SPD_none 111 #undef BL32_BASE 112 #endif /* SPD_none */ 113 #endif 114 115 #define POPLAR_EMMC_DATA_BASE U(0x02200000) 116 #define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE 117 #define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE) 118 #define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE 119 120 #define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000 121 122 /* Page table and MMU setup constants */ 123 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 124 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 125 #define MAX_XLAT_TABLES (4) 126 #define MAX_MMAP_REGIONS (16) 127 128 #define CACHE_WRITEBACK_SHIFT (6) 129 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 130 131 /* Power states */ 132 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) 133 #define PLAT_MAX_OFF_STATE U(2) 134 #define PLAT_MAX_RET_STATE U(1) 135 136 /* Interrupt controller */ 137 #define POPLAR_GICD_BASE GICD_BASE 138 #define POPLAR_GICC_BASE GICC_BASE 139 140 #define POPLAR_G1S_IRQ_PROPS(grp) \ 141 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_LEVEL), \ 143 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_LEVEL), \ 145 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 146 GIC_INTR_CFG_LEVEL), \ 147 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 148 GIC_INTR_CFG_LEVEL), \ 149 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 150 GIC_INTR_CFG_LEVEL), \ 151 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 152 GIC_INTR_CFG_LEVEL), \ 153 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 154 GIC_INTR_CFG_LEVEL), \ 155 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 156 GIC_INTR_CFG_LEVEL), \ 157 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 158 GIC_INTR_CFG_LEVEL), \ 159 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 160 GIC_INTR_CFG_LEVEL), \ 161 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 162 GIC_INTR_CFG_LEVEL), \ 163 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 164 GIC_INTR_CFG_LEVEL), \ 165 INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \ 166 GIC_INTR_CFG_LEVEL) 167 168 #define POPLAR_G0_IRQ_PROPS(grp) 169 170 #endif /* PLATFORM_DEF_H */ 171