1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv3.h> 13 #include "../common/gic_common_private.h" 14 #include "gicv3_private.h" 15 16 static const gicv3_driver_data_t *driver_data; 17 static unsigned int gicv2_compat; 18 19 /* 20 * Redistributor power operations are weakly bound so that they can be 21 * overridden 22 */ 23 #pragma weak gicv3_rdistif_off 24 #pragma weak gicv3_rdistif_on 25 26 /******************************************************************************* 27 * This function initialises the ARM GICv3 driver in EL3 with provided platform 28 * inputs. 29 ******************************************************************************/ 30 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 31 { 32 unsigned int gic_version; 33 34 assert(plat_driver_data); 35 assert(plat_driver_data->gicd_base); 36 assert(plat_driver_data->gicr_base); 37 assert(plat_driver_data->rdistif_num); 38 assert(plat_driver_data->rdistif_base_addrs); 39 40 assert(IS_IN_EL3()); 41 42 /* 43 * The platform should provide a list of at least one type of 44 * interrupts 45 */ 46 assert(plat_driver_data->g0_interrupt_array || 47 plat_driver_data->g1s_interrupt_array); 48 49 /* 50 * If there are no interrupts of a particular type, then the number of 51 * interrupts of that type should be 0 and vice-versa. 52 */ 53 assert(plat_driver_data->g0_interrupt_array ? 54 plat_driver_data->g0_interrupt_num : 55 plat_driver_data->g0_interrupt_num == 0); 56 assert(plat_driver_data->g1s_interrupt_array ? 57 plat_driver_data->g1s_interrupt_num : 58 plat_driver_data->g1s_interrupt_num == 0); 59 60 /* Check for system register support */ 61 #ifdef AARCH32 62 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 63 #else 64 assert(read_id_aa64pfr0_el1() & 65 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 66 #endif /* AARCH32 */ 67 68 /* The GIC version should be 3.0 */ 69 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 70 gic_version >>= PIDR2_ARCH_REV_SHIFT; 71 gic_version &= PIDR2_ARCH_REV_MASK; 72 assert(gic_version == ARCH_REV_GICV3); 73 74 /* 75 * Find out whether the GIC supports the GICv2 compatibility mode. The 76 * ARE_S bit resets to 0 if supported 77 */ 78 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 79 gicv2_compat >>= CTLR_ARE_S_SHIFT; 80 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 81 82 /* 83 * Find the base address of each implemented Redistributor interface. 84 * The number of interfaces should be equal to the number of CPUs in the 85 * system. The memory for saving these addresses has to be allocated by 86 * the platform port 87 */ 88 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 89 plat_driver_data->rdistif_num, 90 plat_driver_data->gicr_base, 91 plat_driver_data->mpidr_to_core_pos); 92 93 driver_data = plat_driver_data; 94 95 /* 96 * The GIC driver data is initialized by the primary CPU with caches 97 * enabled. When the secondary CPU boots up, it initializes the 98 * GICC/GICR interface with the caches disabled. Hence flush the 99 * driver_data to ensure coherency. This is not required if the 100 * platform has HW_ASSISTED_COHERENCY enabled. 101 */ 102 #if !HW_ASSISTED_COHERENCY 103 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 104 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 105 #endif 106 107 INFO("GICv3 %s legacy support detected." 108 " ARM GICV3 driver initialized in EL3\n", 109 gicv2_compat ? "with" : "without"); 110 } 111 112 /******************************************************************************* 113 * This function initialises the GIC distributor interface based upon the data 114 * provided by the platform while initialising the driver. 115 ******************************************************************************/ 116 void gicv3_distif_init(void) 117 { 118 unsigned int bitmap = 0; 119 120 assert(driver_data); 121 assert(driver_data->gicd_base); 122 assert(driver_data->g1s_interrupt_array || 123 driver_data->g0_interrupt_array); 124 125 assert(IS_IN_EL3()); 126 127 /* 128 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 129 * the ARE_S bit. The Distributor might generate a system error 130 * otherwise. 131 */ 132 gicd_clr_ctlr(driver_data->gicd_base, 133 CTLR_ENABLE_G0_BIT | 134 CTLR_ENABLE_G1S_BIT | 135 CTLR_ENABLE_G1NS_BIT, 136 RWP_TRUE); 137 138 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 139 gicd_set_ctlr(driver_data->gicd_base, 140 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 141 142 /* Set the default attribute of all SPIs */ 143 gicv3_spis_configure_defaults(driver_data->gicd_base); 144 145 /* Configure the G1S SPIs */ 146 if (driver_data->g1s_interrupt_array) { 147 gicv3_secure_spis_configure(driver_data->gicd_base, 148 driver_data->g1s_interrupt_num, 149 driver_data->g1s_interrupt_array, 150 INTR_GROUP1S); 151 bitmap |= CTLR_ENABLE_G1S_BIT; 152 } 153 154 /* Configure the G0 SPIs */ 155 if (driver_data->g0_interrupt_array) { 156 gicv3_secure_spis_configure(driver_data->gicd_base, 157 driver_data->g0_interrupt_num, 158 driver_data->g0_interrupt_array, 159 INTR_GROUP0); 160 bitmap |= CTLR_ENABLE_G0_BIT; 161 } 162 163 /* Enable the secure SPIs now that they have been configured */ 164 gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE); 165 } 166 167 /******************************************************************************* 168 * This function initialises the GIC Redistributor interface of the calling CPU 169 * (identified by the 'proc_num' parameter) based upon the data provided by the 170 * platform while initialising the driver. 171 ******************************************************************************/ 172 void gicv3_rdistif_init(unsigned int proc_num) 173 { 174 uintptr_t gicr_base; 175 176 assert(driver_data); 177 assert(proc_num < driver_data->rdistif_num); 178 assert(driver_data->rdistif_base_addrs); 179 assert(driver_data->gicd_base); 180 assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); 181 assert(driver_data->g1s_interrupt_array || 182 driver_data->g0_interrupt_array); 183 184 assert(IS_IN_EL3()); 185 186 /* Power on redistributor */ 187 gicv3_rdistif_on(proc_num); 188 189 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 190 191 /* Set the default attribute of all SGIs and PPIs */ 192 gicv3_ppi_sgi_configure_defaults(gicr_base); 193 194 /* Configure the G1S SGIs/PPIs */ 195 if (driver_data->g1s_interrupt_array) { 196 gicv3_secure_ppi_sgi_configure(gicr_base, 197 driver_data->g1s_interrupt_num, 198 driver_data->g1s_interrupt_array, 199 INTR_GROUP1S); 200 } 201 202 /* Configure the G0 SGIs/PPIs */ 203 if (driver_data->g0_interrupt_array) { 204 gicv3_secure_ppi_sgi_configure(gicr_base, 205 driver_data->g0_interrupt_num, 206 driver_data->g0_interrupt_array, 207 INTR_GROUP0); 208 } 209 } 210 211 /******************************************************************************* 212 * Functions to perform power operations on GIC Redistributor 213 ******************************************************************************/ 214 void gicv3_rdistif_off(unsigned int proc_num) 215 { 216 return; 217 } 218 219 void gicv3_rdistif_on(unsigned int proc_num) 220 { 221 return; 222 } 223 224 /******************************************************************************* 225 * This function enables the GIC CPU interface of the calling CPU using only 226 * system register accesses. 227 ******************************************************************************/ 228 void gicv3_cpuif_enable(unsigned int proc_num) 229 { 230 uintptr_t gicr_base; 231 unsigned int scr_el3; 232 unsigned int icc_sre_el3; 233 234 assert(driver_data); 235 assert(proc_num < driver_data->rdistif_num); 236 assert(driver_data->rdistif_base_addrs); 237 assert(IS_IN_EL3()); 238 239 /* Mark the connected core as awake */ 240 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 241 gicv3_rdistif_mark_core_awake(gicr_base); 242 243 /* Disable the legacy interrupt bypass */ 244 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 245 246 /* 247 * Enable system register access for EL3 and allow lower exception 248 * levels to configure the same for themselves. If the legacy mode is 249 * not supported, the SRE bit is RAO/WI 250 */ 251 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 252 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 253 254 scr_el3 = read_scr_el3(); 255 256 /* 257 * Switch to NS state to write Non secure ICC_SRE_EL1 and 258 * ICC_SRE_EL2 registers. 259 */ 260 write_scr_el3(scr_el3 | SCR_NS_BIT); 261 isb(); 262 263 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 264 write_icc_sre_el1(ICC_SRE_SRE_BIT); 265 isb(); 266 267 /* Switch to secure state. */ 268 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 269 isb(); 270 271 /* Program the idle priority in the PMR */ 272 write_icc_pmr_el1(GIC_PRI_MASK); 273 274 /* Enable Group0 interrupts */ 275 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 276 277 /* Enable Group1 Secure interrupts */ 278 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 279 IGRPEN1_EL3_ENABLE_G1S_BIT); 280 281 /* Write the secure ICC_SRE_EL1 register */ 282 write_icc_sre_el1(ICC_SRE_SRE_BIT); 283 isb(); 284 } 285 286 /******************************************************************************* 287 * This function disables the GIC CPU interface of the calling CPU using 288 * only system register accesses. 289 ******************************************************************************/ 290 void gicv3_cpuif_disable(unsigned int proc_num) 291 { 292 uintptr_t gicr_base; 293 294 assert(driver_data); 295 assert(proc_num < driver_data->rdistif_num); 296 assert(driver_data->rdistif_base_addrs); 297 298 assert(IS_IN_EL3()); 299 300 /* Disable legacy interrupt bypass */ 301 write_icc_sre_el3(read_icc_sre_el3() | 302 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 303 304 /* Disable Group0 interrupts */ 305 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 306 ~IGRPEN1_EL1_ENABLE_G0_BIT); 307 308 /* Disable Group1 Secure and Non-Secure interrupts */ 309 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 310 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 311 IGRPEN1_EL3_ENABLE_G1S_BIT)); 312 313 /* Synchronise accesses to group enable registers */ 314 isb(); 315 316 /* Mark the connected core as asleep */ 317 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 318 gicv3_rdistif_mark_core_asleep(gicr_base); 319 } 320 321 /******************************************************************************* 322 * This function returns the id of the highest priority pending interrupt at 323 * the GIC cpu interface. 324 ******************************************************************************/ 325 unsigned int gicv3_get_pending_interrupt_id(void) 326 { 327 unsigned int id; 328 329 assert(IS_IN_EL3()); 330 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 331 332 /* 333 * If the ID is special identifier corresponding to G1S or G1NS 334 * interrupt, then read the highest pending group 1 interrupt. 335 */ 336 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 337 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 338 339 return id; 340 } 341 342 /******************************************************************************* 343 * This function returns the type of the highest priority pending interrupt at 344 * the GIC cpu interface. The return values can be one of the following : 345 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 346 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 347 * 0 - 1019 : The interrupt type is secure Group 0. 348 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 349 * sufficient priority to be signaled 350 ******************************************************************************/ 351 unsigned int gicv3_get_pending_interrupt_type(void) 352 { 353 assert(IS_IN_EL3()); 354 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 355 } 356 357 /******************************************************************************* 358 * This function returns the type of the interrupt id depending upon the group 359 * this interrupt has been configured under by the interrupt controller i.e. 360 * group0 or group1 Secure / Non Secure. The return value can be one of the 361 * following : 362 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 363 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 364 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 365 * interrupt. 366 ******************************************************************************/ 367 unsigned int gicv3_get_interrupt_type(unsigned int id, 368 unsigned int proc_num) 369 { 370 unsigned int igroup, grpmodr; 371 uintptr_t gicr_base; 372 373 assert(IS_IN_EL3()); 374 assert(driver_data); 375 376 /* Ensure the parameters are valid */ 377 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 378 assert(proc_num < driver_data->rdistif_num); 379 380 /* All LPI interrupts are Group 1 non secure */ 381 if (id >= MIN_LPI_ID) 382 return INTR_GROUP1NS; 383 384 if (id < MIN_SPI_ID) { 385 assert(driver_data->rdistif_base_addrs); 386 gicr_base = driver_data->rdistif_base_addrs[proc_num]; 387 igroup = gicr_get_igroupr0(gicr_base, id); 388 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 389 } else { 390 assert(driver_data->gicd_base); 391 igroup = gicd_get_igroupr(driver_data->gicd_base, id); 392 grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); 393 } 394 395 /* 396 * If the IGROUP bit is set, then it is a Group 1 Non secure 397 * interrupt 398 */ 399 if (igroup) 400 return INTR_GROUP1NS; 401 402 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 403 if (grpmodr) 404 return INTR_GROUP1S; 405 406 /* Else it is a Group 0 Secure interrupt */ 407 return INTR_GROUP0; 408 } 409