| 84597b57 | 12-May-2017 |
Lin Huang <hl@rock-chips.com> |
rockchip: check wakeup cpu when resume
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need
rockchip: check wakeup cpu when resume
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume.
Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com>
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| 4e836d35 | 16-May-2017 |
Lin Huang <hl@rock-chips.com> |
rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, sarad
rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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| ae7a9352 | 22-Dec-2016 |
Xing Zheng <zhengxing@rock-chips.com> |
rockchip: rk3399: sperate the BL31 parameters for sharing
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don'
rockchip: rk3399: sperate the BL31 parameters for sharing
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don't have to hardcode the range in two places.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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| 941c7147 | 24-Feb-2017 |
Xing Zheng <zhengxing@rock-chips.com> |
rockchip: rk3399: configure the DDR secure region for BL31 image
Move the BL31 loaded base address 0x10000 to 0x1000, and configure the the memory range 0~1MB is secure, the goal is that make sure t
rockchip: rk3399: configure the DDR secure region for BL31 image
Move the BL31 loaded base address 0x10000 to 0x1000, and configure the the memory range 0~1MB is secure, the goal is that make sure the BL31 image will be not modified.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
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| 8382e17c | 12-Oct-2016 |
Caesar Wang <wxt@rock-chips.com> |
rockchip: add M0 source code and build system for RK3399
This CL supports add M0 source code to built into the bl31.bin, the goal is that we can load the M0 code binary into SRAM and execute it.
We
rockchip: add M0 source code and build system for RK3399
This CL supports add M0 source code to built into the bl31.bin, the goal is that we can load the M0 code binary into SRAM and execute it.
We need the M0 help us to clean the power_mode_en bit during the AP PMU enter the state machine with interrupt, and avoid to the AP can not exit the loop forever.
Change-Id: I844582c54a1f0d44ca41290d44618df58679f341 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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