1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <m0_ctl.h> 36 #include <plat_private.h> 37 #include <rk3399_def.h> 38 #include <soc.h> 39 40 void m0_init(void) 41 { 42 /* secure config for M0 */ 43 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 44 mmio_write_32(SGRF_BASE + SGRF_SOC_CON6, WMSK_BIT(12)); 45 46 /* set the execute address for M0 */ 47 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 48 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, 49 0xffff, 0)); 50 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 51 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 52 0xf, 0)); 53 54 /* gating disable for M0 */ 55 mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1)); 56 57 /* 58 * To switch the parent to xin24M and div == 1, 59 * 60 * We need to close most of the PLLs and clocks except the OSC 24MHz 61 * durning suspend, and this should be enough to supplies the ddrfreq, 62 * For the simple handle, we just keep the fixed 24MHz to supply the 63 * suspend and ddrfreq directly. 64 */ 65 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, 66 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); 67 } 68 69 void m0_start(void) 70 { 71 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ 72 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); 73 74 /* enable clocks for M0 */ 75 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 76 BITS_WITH_WMASK(0x0, 0x2f, 0)); 77 78 /* start M0 */ 79 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 80 BITS_WITH_WMASK(0x0, 0x24, 0)); 81 } 82 83 void m0_stop(void) 84 { 85 /* stop M0 */ 86 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 87 BITS_WITH_WMASK(0x24, 0x24, 0)); 88 89 /* disable clocks for M0 */ 90 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 91 BITS_WITH_WMASK(0x2f, 0x2f, 0)); 92 } 93 94 void m0_wait_done(void) 95 { 96 while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG) 97 dsb(); 98 } 99