1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <mmio.h> 32 #include <ddr_rk3368.h> 33 #include <debug.h> 34 #include <stdint.h> 35 #include <string.h> 36 #include <platform_def.h> 37 #include <pmu.h> 38 #include <rk3368_def.h> 39 #include <soc.h> 40 41 /* GRF_SOC_STATUS0 */ 42 #define DPLL_LOCK (0x1 << 2) 43 44 /* GRF_DDRC0_CON0 */ 45 #define GRF_DDR_16BIT_EN (((0x1 << 3) << 16) | (0x1 << 3)) 46 #define GRF_DDR_32BIT_EN (((0x1 << 3) << 16) | (0x0 << 3)) 47 #define GRF_MOBILE_DDR_EN (((0x1 << 4) << 16) | (0x1 << 4)) 48 #define GRF_MOBILE_DDR_DISB (((0x1 << 4) << 16) | (0x0 << 4)) 49 #define GRF_DDR3_EN (((0x1 << 2) << 16) | (0x1 << 2)) 50 #define GRF_LPDDR2_3_EN (((0x1 << 2) << 16) | (0x0 << 2)) 51 52 /* PMUGRF_SOC_CON0 */ 53 #define ddrphy_bufferen_io_en(n) ((0x1 << (9 + 16)) | (n << 9)) 54 #define ddrphy_bufferen_core_en(n) ((0x1 << (8 + 16)) | (n << 8)) 55 56 struct PCTRL_TIMING_TAG { 57 uint32_t ddrfreq; 58 uint32_t TOGCNT1U; 59 uint32_t TINIT; 60 uint32_t TRSTH; 61 uint32_t TOGCNT100N; 62 uint32_t TREFI; 63 uint32_t TMRD; 64 uint32_t TRFC; 65 uint32_t TRP; 66 uint32_t TRTW; 67 uint32_t TAL; 68 uint32_t TCL; 69 uint32_t TCWL; 70 uint32_t TRAS; 71 uint32_t TRC; 72 uint32_t TRCD; 73 uint32_t TRRD; 74 uint32_t TRTP; 75 uint32_t TWR; 76 uint32_t TWTR; 77 uint32_t TEXSR; 78 uint32_t TXP; 79 uint32_t TXPDLL; 80 uint32_t TZQCS; 81 uint32_t TZQCSI; 82 uint32_t TDQS; 83 uint32_t TCKSRE; 84 uint32_t TCKSRX; 85 uint32_t TCKE; 86 uint32_t TMOD; 87 uint32_t TRSTL; 88 uint32_t TZQCL; 89 uint32_t TMRR; 90 uint32_t TCKESR; 91 uint32_t TDPD; 92 uint32_t TREFI_MEM_DDR3; 93 }; 94 95 struct MSCH_SAVE_REG_TAG { 96 uint32_t ddrconf; 97 uint32_t ddrtiming; 98 uint32_t ddrmode; 99 uint32_t readlatency; 100 uint32_t activate; 101 uint32_t devtodev; 102 }; 103 104 /* ddr suspend need save reg */ 105 struct PCTL_SAVE_REG_TAG { 106 uint32_t SCFG; 107 uint32_t CMDTSTATEN; 108 uint32_t MCFG1; 109 uint32_t MCFG; 110 uint32_t PPCFG; 111 struct PCTRL_TIMING_TAG pctl_timing; 112 /* DFI Control Registers */ 113 uint32_t DFITCTRLDELAY; 114 uint32_t DFIODTCFG; 115 uint32_t DFIODTCFG1; 116 uint32_t DFIODTRANKMAP; 117 /* DFI Write Data Registers */ 118 uint32_t DFITPHYWRDATA; 119 uint32_t DFITPHYWRLAT; 120 uint32_t DFITPHYWRDATALAT; 121 /* DFI Read Data Registers */ 122 uint32_t DFITRDDATAEN; 123 uint32_t DFITPHYRDLAT; 124 /* DFI Update Registers */ 125 uint32_t DFITPHYUPDTYPE0; 126 uint32_t DFITPHYUPDTYPE1; 127 uint32_t DFITPHYUPDTYPE2; 128 uint32_t DFITPHYUPDTYPE3; 129 uint32_t DFITCTRLUPDMIN; 130 uint32_t DFITCTRLUPDMAX; 131 uint32_t DFITCTRLUPDDLY; 132 uint32_t DFIUPDCFG; 133 uint32_t DFITREFMSKI; 134 uint32_t DFITCTRLUPDI; 135 /* DFI Status Registers */ 136 uint32_t DFISTCFG0; 137 uint32_t DFISTCFG1; 138 uint32_t DFITDRAMCLKEN; 139 uint32_t DFITDRAMCLKDIS; 140 uint32_t DFISTCFG2; 141 /* DFI Low Power Register */ 142 uint32_t DFILPCFG0; 143 }; 144 145 struct DDRPHY_SAVE_REG_TAG { 146 uint32_t PHY_REG0; 147 uint32_t PHY_REG1; 148 uint32_t PHY_REGB; 149 uint32_t PHY_REGC; 150 uint32_t PHY_REG11; 151 uint32_t PHY_REG13; 152 uint32_t PHY_REG14; 153 uint32_t PHY_REG16; 154 uint32_t PHY_REG20; 155 uint32_t PHY_REG21; 156 uint32_t PHY_REG26; 157 uint32_t PHY_REG27; 158 uint32_t PHY_REG28; 159 uint32_t PHY_REG30; 160 uint32_t PHY_REG31; 161 uint32_t PHY_REG36; 162 uint32_t PHY_REG37; 163 uint32_t PHY_REG38; 164 uint32_t PHY_REG40; 165 uint32_t PHY_REG41; 166 uint32_t PHY_REG46; 167 uint32_t PHY_REG47; 168 uint32_t PHY_REG48; 169 uint32_t PHY_REG50; 170 uint32_t PHY_REG51; 171 uint32_t PHY_REG56; 172 uint32_t PHY_REG57; 173 uint32_t PHY_REG58; 174 uint32_t PHY_REGDLL; 175 uint32_t PHY_REGEC; 176 uint32_t PHY_REGED; 177 uint32_t PHY_REGEE; 178 uint32_t PHY_REGEF; 179 uint32_t PHY_REGFB; 180 uint32_t PHY_REGFC; 181 uint32_t PHY_REGFD; 182 uint32_t PHY_REGFE; 183 }; 184 185 struct BACKUP_REG_TAG { 186 uint32_t tag; 187 uint32_t pctladdr; 188 struct PCTL_SAVE_REG_TAG pctl; 189 uint32_t phyaddr; 190 struct DDRPHY_SAVE_REG_TAG phy; 191 uint32_t nocaddr; 192 struct MSCH_SAVE_REG_TAG noc; 193 uint32_t pllselect; 194 uint32_t phypllockaddr; 195 uint32_t phyplllockmask; 196 uint32_t phyplllockval; 197 uint32_t pllpdstat; 198 uint32_t dpllmodeaddr; 199 uint32_t dpllslowmode; 200 uint32_t dpllnormalmode; 201 uint32_t dpllresetaddr; 202 uint32_t dpllreset; 203 uint32_t dplldereset; 204 uint32_t dpllconaddr; 205 uint32_t dpllcon[4]; 206 uint32_t dplllockaddr; 207 uint32_t dplllockmask; 208 uint32_t dplllockval; 209 uint32_t ddrpllsrcdivaddr; 210 uint32_t ddrpllsrcdiv; 211 uint32_t retendisaddr; 212 uint32_t retendisval; 213 uint32_t grfregaddr; 214 uint32_t grfddrcreg; 215 uint32_t crupctlphysoftrstaddr; 216 uint32_t cruresetpctlphy; 217 uint32_t cruderesetphy; 218 uint32_t cruderesetpctlphy; 219 uint32_t physoftrstaddr; 220 uint32_t endtag; 221 }; 222 223 static uint32_t ddr_get_phy_pll_freq(void) 224 { 225 uint32_t ret = 0; 226 uint32_t fb_div, pre_div; 227 228 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); 229 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; 230 231 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; 232 ret = 2 * 24 * fb_div / (4 * pre_div); 233 234 return ret; 235 } 236 237 static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words) 238 { 239 uint32_t i; 240 241 for (i = 0; i < words; i++) 242 pdest[i] = psrc[i]; 243 } 244 245 static void ddr_get_dpll_cfg(uint32_t *p) 246 { 247 uint32_t nmhz, NO, NF, NR; 248 249 nmhz = ddr_get_phy_pll_freq(); 250 if (nmhz <= 150) 251 NO = 6; 252 else if (nmhz <= 250) 253 NO = 4; 254 else if (nmhz <= 500) 255 NO = 2; 256 else 257 NO = 1; 258 259 NR = 1; 260 NF = 2 * nmhz * NR * NO / 24; 261 262 p[0] = SET_NR(NR) | SET_NO(NO); 263 p[1] = SET_NF(NF); 264 p[2] = SET_NB(NF / 2); 265 } 266 267 void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr) 268 { 269 struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr; 270 struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl; 271 272 p_ddr_reg->tag = 0x56313031; 273 p_ddr_reg->pctladdr = DDR_PCTL_BASE; 274 p_ddr_reg->phyaddr = DDR_PHY_BASE; 275 p_ddr_reg->nocaddr = SERVICE_BUS_BASE; 276 277 /* PCTLR */ 278 ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U, 279 (uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35); 280 pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE; 281 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG); 282 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + 283 DDR_PCTL_CMDTSTATEN); 284 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1); 285 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG); 286 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG); 287 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE + 288 DDR_PCTL_TOGCNT1U * 2); 289 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE + 290 DDR_PCTL_DFITCTRLDELAY); 291 pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG); 292 pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE + 293 DDR_PCTL_DFIODTCFG1); 294 pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE + 295 DDR_PCTL_DFIODTRANKMAP); 296 pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE + 297 DDR_PCTL_DFITPHYWRDATA); 298 pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE + 299 DDR_PCTL_DFITPHYWRLAT); 300 pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE + 301 DDR_PCTL_DFITPHYWRDATALAT); 302 pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE + 303 DDR_PCTL_DFITRDDATAEN); 304 pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE + 305 DDR_PCTL_DFITPHYRDLAT); 306 pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE + 307 DDR_PCTL_DFITPHYUPDTYPE0); 308 pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE + 309 DDR_PCTL_DFITPHYUPDTYPE1); 310 pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE + 311 DDR_PCTL_DFITPHYUPDTYPE2); 312 pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE + 313 DDR_PCTL_DFITPHYUPDTYPE3); 314 pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE + 315 DDR_PCTL_DFITCTRLUPDMIN); 316 pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE + 317 DDR_PCTL_DFITCTRLUPDMAX); 318 pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE + 319 DDR_PCTL_DFITCTRLUPDDLY); 320 321 pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG); 322 pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE + 323 DDR_PCTL_DFITREFMSKI); 324 pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE + 325 DDR_PCTL_DFITCTRLUPDI); 326 pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0); 327 pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1); 328 pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE + 329 DDR_PCTL_DFITDRAMCLKEN); 330 pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE + 331 DDR_PCTL_DFITDRAMCLKDIS); 332 pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2); 333 pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0); 334 335 /* PHY */ 336 p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0); 337 p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1); 338 p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB); 339 p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC); 340 p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11); 341 p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13); 342 p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14); 343 p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16); 344 p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20); 345 p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21); 346 p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26); 347 p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27); 348 p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28); 349 p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30); 350 p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31); 351 p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36); 352 p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37); 353 p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38); 354 p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40); 355 p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41); 356 p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46); 357 p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47); 358 p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48); 359 p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50); 360 p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51); 361 p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56); 362 p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57); 363 p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58); 364 p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE + 365 DDR_PHY_REGDLL); 366 p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); 367 p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED); 368 p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE); 369 p_ddr_reg->phy.PHY_REGEF = 0; 370 371 if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) { 372 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + 373 DDR_PHY_REG2C); 374 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + 375 DDR_PHY_REG3C); 376 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + 377 DDR_PHY_REG4C); 378 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE + 379 DDR_PHY_REG5C); 380 } else { 381 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + 382 DDR_PHY_REGFB); 383 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + 384 DDR_PHY_REGFC); 385 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + 386 DDR_PHY_REGFD); 387 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE + 388 DDR_PHY_REGFE); 389 } 390 391 /* NOC */ 392 p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF); 393 p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE + 394 MSCH_DDRTIMING); 395 p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE); 396 p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE + 397 MSCH_READLATENCY); 398 p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE + 399 MSCH_ACTIVATE); 400 p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE + 401 MSCH_DEVTODEV); 402 403 p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1; 404 p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0; 405 p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK; 406 p_ddr_reg->phyplllockval = 0; 407 408 /* PLLPD */ 409 p_ddr_reg->pllpdstat = pllpdstat; 410 /* DPLL */ 411 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); 412 /* slow mode and power on */ 413 p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN; 414 p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE; 415 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); 416 p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL; 417 p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET; 418 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); 419 420 if (p_ddr_reg->pllselect == 0) { 421 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + 422 PLL_CONS(DPLL_ID, 0)) 423 & 0xffff) | 424 (0xFFFF << 16); 425 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + 426 PLL_CONS(DPLL_ID, 1)) 427 & 0xffff); 428 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + 429 PLL_CONS(DPLL_ID, 2)) 430 & 0xffff); 431 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE + 432 PLL_CONS(DPLL_ID, 3)) 433 & 0xffff) | 434 (0xFFFF << 16); 435 } else { 436 ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]); 437 } 438 439 p_ddr_reg->pllselect = 0; 440 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); 441 p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK; 442 p_ddr_reg->dplllockval = DPLL_STATUS_LOCK; 443 444 /* SET_DDR_PLL_SRC */ 445 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13); 446 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13)) 447 & DDR_PLL_SRC_MASK) 448 | (DDR_PLL_SRC_MASK << 16); 449 p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM; 450 p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE; 451 p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0; 452 p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) & 453 DDR_PLL_SRC_MASK) | 454 (DDR_PLL_SRC_MASK << 16); 455 456 /* pctl phy soft reset */ 457 p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10); 458 p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) | 459 DDRCTRL0_SRSTN_REQ(1) | 460 DDRPHY0_PSRSTN_REQ(1) | 461 DDRPHY0_SRSTN_REQ(1); 462 p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) | 463 DDRCTRL0_SRSTN_REQ(1) | 464 DDRPHY0_PSRSTN_REQ(0) | 465 DDRPHY0_SRSTN_REQ(0); 466 467 p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) | 468 DDRCTRL0_SRSTN_REQ(0) | 469 DDRPHY0_PSRSTN_REQ(0) | 470 DDRPHY0_SRSTN_REQ(0); 471 472 p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0; 473 474 p_ddr_reg->endtag = 0xFFFFFFFF; 475 } 476 477 /* 478 * "rk3368_ddr_reg_resume_V1.05.bin" is an executable bin which is generated 479 * by ARM DS5 for resuming ddr controller. If the soc wakes up from system 480 * suspend, ddr needs to be resumed and the resuming code needs to be run in 481 * sram. But there is not a way to pointing the resuming code to the PMUSRAM 482 * when linking .o files of bl31, so we use the 483 * "rk3368_ddr_reg_resume_V1.05.bin" whose code is position-independent and 484 * it can be loaded anywhere and run. 485 */ 486 static __aligned(4) unsigned int ddr_reg_resume[] = { 487 #include "rk3368_ddr_reg_resume_V1.05.bin" 488 }; 489 490 uint32_t ddr_get_resume_code_size(void) 491 { 492 return sizeof(ddr_reg_resume); 493 } 494 495 uint32_t ddr_get_resume_data_size(void) 496 { 497 return sizeof(struct BACKUP_REG_TAG); 498 } 499 500 uint32_t *ddr_get_resume_code_base(void) 501 { 502 return (unsigned int *)ddr_reg_resume; 503 } 504