1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <mmio.h> 34 #include <m0_ctl.h> 35 #include <plat_private.h> 36 #include "dfs.h" 37 #include "dram.h" 38 #include "dram_spec_timing.h" 39 #include "string.h" 40 #include "soc.h" 41 #include "pmu.h" 42 43 #include <delay_timer.h> 44 45 #define ENPER_CS_TRAINING_FREQ (933) 46 #define PHY_DLL_BYPASS_FREQ (260) 47 48 static const struct pll_div dpll_rates_table[] = { 49 50 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 51 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 52 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 53 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 54 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 55 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 56 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 57 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 58 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 59 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 60 }; 61 62 struct rk3399_dram_status { 63 uint32_t current_index; 64 uint32_t index_freq[2]; 65 uint32_t low_power_stat; 66 struct timing_related_config timing_config; 67 struct drv_odt_lp_config drv_odt_lp_cfg; 68 }; 69 70 static struct rk3399_dram_status rk3399_dram_status; 71 static uint32_t wrdqs_delay_val[2][2][4]; 72 73 static struct rk3399_sdram_default_config ddr3_default_config = { 74 .bl = 8, 75 .ap = 0, 76 .burst_ref_cnt = 1, 77 .zqcsi = 0 78 }; 79 80 static struct rk3399_sdram_default_config lpddr3_default_config = { 81 .bl = 8, 82 .ap = 0, 83 .burst_ref_cnt = 1, 84 .zqcsi = 0 85 }; 86 87 static struct rk3399_sdram_default_config lpddr4_default_config = { 88 .bl = 16, 89 .ap = 0, 90 .caodt = 240, 91 .burst_ref_cnt = 1, 92 .zqcsi = 0 93 }; 94 95 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 96 uint8_t channel, uint8_t cs) 97 { 98 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 99 uint32_t bandwidth; 100 uint32_t die_bandwidth; 101 uint32_t die; 102 uint32_t cs_cap; 103 uint32_t row; 104 105 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 106 bandwidth = 8 * (1 << ch->bw); 107 die_bandwidth = 8 * (1 << ch->dbw); 108 die = bandwidth / die_bandwidth; 109 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 110 (bandwidth / 16))); 111 if (ch->row_3_4) 112 cs_cap = cs_cap * 3 / 4; 113 114 return (cs_cap / die); 115 } 116 117 static void get_dram_drv_odt_val(uint32_t dram_type, 118 struct drv_odt_lp_config *drv_config) 119 { 120 uint32_t tmp; 121 uint32_t mr1_val, mr3_val, mr11_val; 122 123 switch (dram_type) { 124 case DDR3: 125 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 126 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 127 if (tmp) 128 drv_config->dram_side_drv = 34; 129 else 130 drv_config->dram_side_drv = 40; 131 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 132 ((mr1_val >> 7) & 1); 133 if (tmp == 0) 134 drv_config->dram_side_dq_odt = 0; 135 else if (tmp == 1) 136 drv_config->dram_side_dq_odt = 60; 137 else if (tmp == 3) 138 drv_config->dram_side_dq_odt = 40; 139 else 140 drv_config->dram_side_dq_odt = 120; 141 break; 142 case LPDDR3: 143 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 144 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 145 if (mr3_val == 0xb) 146 drv_config->dram_side_drv = 3448; 147 else if (mr3_val == 0xa) 148 drv_config->dram_side_drv = 4048; 149 else if (mr3_val == 0x9) 150 drv_config->dram_side_drv = 3440; 151 else if (mr3_val == 0x4) 152 drv_config->dram_side_drv = 60; 153 else if (mr3_val == 0x3) 154 drv_config->dram_side_drv = 48; 155 else if (mr3_val == 0x2) 156 drv_config->dram_side_drv = 40; 157 else 158 drv_config->dram_side_drv = 34; 159 160 if (mr11_val == 1) 161 drv_config->dram_side_dq_odt = 60; 162 else if (mr11_val == 2) 163 drv_config->dram_side_dq_odt = 120; 164 else if (mr11_val == 0) 165 drv_config->dram_side_dq_odt = 0; 166 else 167 drv_config->dram_side_dq_odt = 240; 168 break; 169 case LPDDR4: 170 default: 171 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 172 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 173 174 if ((mr3_val == 0) || (mr3_val == 7)) 175 drv_config->dram_side_drv = 40; 176 else 177 drv_config->dram_side_drv = 240 / mr3_val; 178 179 tmp = mr11_val & 0x7; 180 if ((tmp == 7) || (tmp == 0)) 181 drv_config->dram_side_dq_odt = 0; 182 else 183 drv_config->dram_side_dq_odt = 240 / tmp; 184 185 tmp = (mr11_val >> 4) & 0x7; 186 if ((tmp == 7) || (tmp == 0)) 187 drv_config->dram_side_ca_odt = 0; 188 else 189 drv_config->dram_side_ca_odt = 240 / tmp; 190 break; 191 } 192 } 193 194 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 195 struct rk3399_sdram_params *sdram_params, 196 struct drv_odt_lp_config *drv_config) 197 { 198 uint32_t i, j; 199 200 for (i = 0; i < sdram_params->num_channels; i++) { 201 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 202 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 203 for (j = 0; j < sdram_params->ch[i].rank; j++) { 204 ptiming_config->dram_info[i].per_die_capability[j] = 205 get_cs_die_capability(sdram_params, i, j); 206 } 207 } 208 ptiming_config->dram_type = sdram_params->dramtype; 209 ptiming_config->ch_cnt = sdram_params->num_channels; 210 switch (sdram_params->dramtype) { 211 case DDR3: 212 ptiming_config->bl = ddr3_default_config.bl; 213 ptiming_config->ap = ddr3_default_config.ap; 214 break; 215 case LPDDR3: 216 ptiming_config->bl = lpddr3_default_config.bl; 217 ptiming_config->ap = lpddr3_default_config.ap; 218 break; 219 case LPDDR4: 220 ptiming_config->bl = lpddr4_default_config.bl; 221 ptiming_config->ap = lpddr4_default_config.ap; 222 ptiming_config->rdbi = 0; 223 ptiming_config->wdbi = 0; 224 break; 225 } 226 ptiming_config->dramds = drv_config->dram_side_drv; 227 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 228 ptiming_config->caodt = drv_config->dram_side_ca_odt; 229 } 230 231 struct lat_adj_pair { 232 uint32_t cl; 233 uint32_t rdlat_adj; 234 uint32_t cwl; 235 uint32_t wrlat_adj; 236 }; 237 238 const struct lat_adj_pair ddr3_lat_adj[] = { 239 {6, 5, 5, 4}, 240 {8, 7, 6, 5}, 241 {10, 9, 7, 6}, 242 {11, 9, 8, 7}, 243 {13, 0xb, 9, 8}, 244 {14, 0xb, 0xa, 9} 245 }; 246 247 const struct lat_adj_pair lpddr3_lat_adj[] = { 248 {3, 2, 1, 0}, 249 {6, 5, 3, 2}, 250 {8, 7, 4, 3}, 251 {9, 8, 5, 4}, 252 {10, 9, 6, 5}, 253 {11, 9, 6, 5}, 254 {12, 0xa, 6, 5}, 255 {14, 0xc, 8, 7}, 256 {16, 0xd, 8, 7} 257 }; 258 259 const struct lat_adj_pair lpddr4_lat_adj[] = { 260 {6, 5, 4, 2}, 261 {10, 9, 6, 4}, 262 {14, 0xc, 8, 6}, 263 {20, 0x11, 0xa, 8}, 264 {24, 0x15, 0xc, 0xa}, 265 {28, 0x18, 0xe, 0xc}, 266 {32, 0x1b, 0x10, 0xe}, 267 {36, 0x1e, 0x12, 0x10} 268 }; 269 270 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 271 { 272 const struct lat_adj_pair *p; 273 uint32_t cnt; 274 uint32_t i; 275 276 if (dram_type == DDR3) { 277 p = ddr3_lat_adj; 278 cnt = ARRAY_SIZE(ddr3_lat_adj); 279 } else if (dram_type == LPDDR3) { 280 p = lpddr3_lat_adj; 281 cnt = ARRAY_SIZE(lpddr3_lat_adj); 282 } else { 283 p = lpddr4_lat_adj; 284 cnt = ARRAY_SIZE(lpddr4_lat_adj); 285 } 286 287 for (i = 0; i < cnt; i++) { 288 if (cl == p[i].cl) 289 return p[i].rdlat_adj; 290 } 291 /* fail */ 292 return 0xff; 293 } 294 295 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 296 { 297 const struct lat_adj_pair *p; 298 uint32_t cnt; 299 uint32_t i; 300 301 if (dram_type == DDR3) { 302 p = ddr3_lat_adj; 303 cnt = ARRAY_SIZE(ddr3_lat_adj); 304 } else if (dram_type == LPDDR3) { 305 p = lpddr3_lat_adj; 306 cnt = ARRAY_SIZE(lpddr3_lat_adj); 307 } else { 308 p = lpddr4_lat_adj; 309 cnt = ARRAY_SIZE(lpddr4_lat_adj); 310 } 311 312 for (i = 0; i < cnt; i++) { 313 if (cwl == p[i].cwl) 314 return p[i].wrlat_adj; 315 } 316 /* fail */ 317 return 0xff; 318 } 319 320 #define PI_REGS_DIMM_SUPPORT (0) 321 #define PI_ADD_LATENCY (0) 322 #define PI_DOUBLEFREEK (1) 323 324 #define PI_PAD_DELAY_PS_VALUE (1000) 325 #define PI_IE_ENABLE_VALUE (3000) 326 #define PI_TSEL_ENABLE_VALUE (700) 327 328 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 329 { 330 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 331 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 332 extra_adder, tsel_enable; 333 334 ie_enable = PI_IE_ENABLE_VALUE; 335 tsel_enable = PI_TSEL_ENABLE_VALUE; 336 337 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 338 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 339 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 340 delay_adder++; 341 hs_offset = 0; 342 tsel_adder = 0; 343 extra_adder = 0; 344 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 345 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 346 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 347 tsel_adder++; 348 delay_adder = delay_adder - 1; 349 if (tsel_adder > delay_adder) 350 extra_adder = tsel_adder - delay_adder; 351 else 352 extra_adder = 0; 353 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 354 hs_offset = 2; 355 else 356 hs_offset = 1; 357 358 if (delay_adder > (rdlat - 1 - hs_offset)) { 359 rdlat = rdlat - tsel_adder; 360 } else { 361 if ((rdlat - delay_adder) < 2) 362 rdlat = 2; 363 else 364 rdlat = rdlat - delay_adder - extra_adder; 365 } 366 367 return rdlat; 368 } 369 370 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 371 struct timing_related_config *timing_config) 372 { 373 uint32_t tmp; 374 375 if (timing_config->dram_type == LPDDR3) { 376 tmp = pdram_timing->cl; 377 if (tmp >= 14) 378 tmp = 8; 379 else if (tmp >= 10) 380 tmp = 6; 381 else if (tmp == 9) 382 tmp = 5; 383 else if (tmp == 8) 384 tmp = 4; 385 else if (tmp == 6) 386 tmp = 3; 387 else 388 tmp = 1; 389 } else { 390 tmp = 1; 391 } 392 393 return tmp; 394 } 395 396 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 397 struct timing_related_config *timing_config) 398 { 399 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 400 } 401 402 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 403 struct timing_related_config *timing_config) 404 { 405 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 406 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 407 uint32_t mem_delay_ps, round_trip_ps; 408 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 409 410 ie_enable = PI_IE_ENABLE_VALUE; 411 412 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 413 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 414 delay_adder++; 415 delay_adder = delay_adder - 1; 416 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 417 hs_offset = 2; 418 else 419 hs_offset = 1; 420 421 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 422 423 if (delay_adder > (cas_lat - 1 - hs_offset)) { 424 ie_delay_adder = 0; 425 } else { 426 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 427 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 428 ie_delay_adder++; 429 } 430 431 if (timing_config->dram_type == DDR3) { 432 mem_delay_ps = 0; 433 } else if (timing_config->dram_type == LPDDR4) { 434 mem_delay_ps = 3600; 435 } else if (timing_config->dram_type == LPDDR3) { 436 mem_delay_ps = 5500; 437 } else { 438 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 439 return 0; 440 } 441 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 442 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 443 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 444 delay_adder++; 445 446 phy_internal_delay = 5 + 2 + 4; 447 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 448 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 449 lpddr_adder++; 450 dfi_adder = 0; 451 phy_internal_delay = phy_internal_delay + 2; 452 rdlat_delay = delay_adder + phy_internal_delay + 453 ie_delay_adder + lpddr_adder + dfi_adder; 454 455 rdlat_delay = rdlat_delay + 2; 456 return rdlat_delay; 457 } 458 459 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 460 struct timing_related_config *timing_config) 461 { 462 uint32_t tmp, todtoff_min_ps; 463 464 if (timing_config->dram_type == LPDDR3) 465 todtoff_min_ps = 2500; 466 else if (timing_config->dram_type == LPDDR4) 467 todtoff_min_ps = 1500; 468 else 469 todtoff_min_ps = 0; 470 /* todtoff_min */ 471 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 472 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 473 tmp++; 474 return tmp; 475 } 476 477 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 478 struct timing_related_config *timing_config) 479 { 480 uint32_t tmp, todtoff_max_ps; 481 482 if ((timing_config->dram_type == LPDDR4) 483 || (timing_config->dram_type == LPDDR3)) 484 todtoff_max_ps = 3500; 485 else 486 todtoff_max_ps = 0; 487 488 /* todtoff_max */ 489 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 490 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 491 tmp++; 492 return tmp; 493 } 494 495 static void gen_rk3399_ctl_params_f0(struct timing_related_config 496 *timing_config, 497 struct dram_timing_t *pdram_timing) 498 { 499 uint32_t i; 500 uint32_t tmp, tmp1; 501 502 for (i = 0; i < timing_config->ch_cnt; i++) { 503 if (timing_config->dram_type == DDR3) { 504 tmp = ((700000 + 10) * timing_config->freq + 505 999) / 1000; 506 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 507 pdram_timing->tmod + pdram_timing->tzqinit; 508 mmio_write_32(CTL_REG(i, 5), tmp); 509 510 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 511 pdram_timing->tdllk); 512 513 mmio_write_32(CTL_REG(i, 32), 514 (pdram_timing->tmod << 8) | 515 pdram_timing->tmrd); 516 517 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 518 (pdram_timing->txsr - 519 pdram_timing->trcd) << 16); 520 } else if (timing_config->dram_type == LPDDR4) { 521 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 522 pdram_timing->tinit3); 523 mmio_write_32(CTL_REG(i, 32), 524 (pdram_timing->tmrd << 8) | 525 pdram_timing->tmrd); 526 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 527 pdram_timing->txsr << 16); 528 } else { 529 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 530 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 531 mmio_write_32(CTL_REG(i, 32), 532 (pdram_timing->tmrd << 8) | 533 pdram_timing->tmrd); 534 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 535 pdram_timing->txsr << 16); 536 } 537 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 538 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 539 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 540 ((pdram_timing->cl * 2) << 16)); 541 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 542 (pdram_timing->cwl << 24)); 543 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 544 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 545 (pdram_timing->trc << 24) | 546 (pdram_timing->trrd << 16)); 547 mmio_write_32(CTL_REG(i, 27), 548 (pdram_timing->tfaw << 24) | 549 (pdram_timing->trppb << 16) | 550 (pdram_timing->twtr << 8) | 551 pdram_timing->tras_min); 552 553 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 554 max(4, pdram_timing->trtp) << 24); 555 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 556 pdram_timing->tras_max); 557 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 558 max(1, pdram_timing->tckesr)); 559 mmio_clrsetbits_32(CTL_REG(i, 39), 560 (0x3f << 16) | (0xff << 8), 561 (pdram_timing->twr << 16) | 562 (pdram_timing->trcd << 8)); 563 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 564 pdram_timing->tmrz << 16); 565 tmp = pdram_timing->tdal ? pdram_timing->tdal : 566 (pdram_timing->twr + pdram_timing->trp); 567 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 568 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 569 mmio_write_32(CTL_REG(i, 48), 570 ((pdram_timing->trefi - 8) << 16) | 571 pdram_timing->trfc); 572 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 573 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 574 pdram_timing->txpdll << 16); 575 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 576 pdram_timing->tcscke << 24); 577 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 578 mmio_write_32(CTL_REG(i, 56), 579 (pdram_timing->tzqcke << 24) | 580 (pdram_timing->tmrwckel << 16) | 581 (pdram_timing->tckehcs << 8) | 582 pdram_timing->tckelcs); 583 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 584 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 585 (pdram_timing->tckehcmd << 24) | 586 (pdram_timing->tckelcmd << 16)); 587 mmio_write_32(CTL_REG(i, 63), 588 (pdram_timing->tckelpd << 24) | 589 (pdram_timing->tescke << 16) | 590 (pdram_timing->tsr << 8) | 591 pdram_timing->tckckel); 592 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 593 (pdram_timing->tcmdcke << 8) | 594 pdram_timing->tcsckeh); 595 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 596 (pdram_timing->tcksrx << 16) | 597 (pdram_timing->tcksre << 8)); 598 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 599 (timing_config->dllbp << 24)); 600 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 601 (pdram_timing->tvrcg_enable << 16)); 602 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 603 pdram_timing->tvrcg_disable); 604 mmio_write_32(CTL_REG(i, 124), 605 (pdram_timing->tvref_long << 16) | 606 (pdram_timing->tckfspx << 8) | 607 pdram_timing->tckfspe); 608 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 609 pdram_timing->mr[0]); 610 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 611 pdram_timing->mr[2]); 612 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 613 pdram_timing->mr[3]); 614 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 615 pdram_timing->mr11 << 24); 616 mmio_write_32(CTL_REG(i, 147), 617 (pdram_timing->mr[1] << 16) | 618 pdram_timing->mr[0]); 619 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 620 pdram_timing->mr[2]); 621 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 622 pdram_timing->mr[3]); 623 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 624 pdram_timing->mr11 << 24); 625 if (timing_config->dram_type == LPDDR4) { 626 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 627 pdram_timing->mr12 << 16); 628 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 629 pdram_timing->mr14 << 16); 630 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 631 pdram_timing->mr22 << 16); 632 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 633 pdram_timing->mr12 << 16); 634 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 635 pdram_timing->mr14 << 16); 636 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 637 pdram_timing->mr22 << 16); 638 } 639 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 640 pdram_timing->tzqinit << 8); 641 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 642 (pdram_timing->tzqinit / 2)); 643 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 644 pdram_timing->tzqcal); 645 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 646 pdram_timing->todton << 8); 647 648 if (timing_config->odt) { 649 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 650 if (timing_config->freq < 400) 651 tmp = 4 << 24; 652 else 653 tmp = 8 << 24; 654 } else { 655 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 656 tmp = 2 << 24; 657 } 658 659 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 660 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 661 (pdram_timing->tdqsck << 16) | 662 (pdram_timing->tdqsck_max << 8)); 663 tmp = 664 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 665 << 8) | get_rdlat_adj(timing_config->dram_type, 666 pdram_timing->cl); 667 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 668 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 669 (4 * pdram_timing->trefi) << 16); 670 671 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 672 (2 * pdram_timing->trefi) & 0xffff); 673 674 if ((timing_config->dram_type == LPDDR3) || 675 (timing_config->dram_type == LPDDR4)) { 676 tmp = get_pi_wrlat(pdram_timing, timing_config); 677 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 678 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 679 } else { 680 tmp = 0; 681 } 682 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 683 (tmp & 0x3f) << 16); 684 685 if ((timing_config->dram_type == LPDDR3) || 686 (timing_config->dram_type == LPDDR4)) { 687 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 688 tmp = pdram_timing->cl + 689 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 690 /* todtoff_max */ 691 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 692 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 693 } else { 694 tmp = pdram_timing->cl - pdram_timing->cwl; 695 } 696 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 697 (tmp & 0x3f) << 8); 698 699 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 700 (get_pi_tdfi_phy_rdlat(pdram_timing, 701 timing_config) & 702 0xff) << 16); 703 704 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 705 (2 * pdram_timing->trefi) & 0xffff); 706 707 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 708 (2 * pdram_timing->trefi) & 0xffff); 709 710 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 711 712 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 713 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 714 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 715 tmp1++; 716 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 717 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 718 719 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 720 tmp = tmp + 18; 721 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 722 723 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 724 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 725 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 726 if (tmp1 == 0) 727 tmp = 0; 728 else if (tmp1 < 5) 729 tmp = tmp1 - 1; 730 else 731 tmp = tmp1 - 5; 732 } else { 733 tmp = tmp1 - 2; 734 } 735 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 736 737 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 738 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 739 (pdram_timing->cl >= 5)) 740 tmp = pdram_timing->cl - 5; 741 else 742 tmp = pdram_timing->cl - 2; 743 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 744 } 745 } 746 747 static void gen_rk3399_ctl_params_f1(struct timing_related_config 748 *timing_config, 749 struct dram_timing_t *pdram_timing) 750 { 751 uint32_t i; 752 uint32_t tmp, tmp1; 753 754 for (i = 0; i < timing_config->ch_cnt; i++) { 755 if (timing_config->dram_type == DDR3) { 756 tmp = 757 ((700000 + 10) * timing_config->freq + 999) / 1000; 758 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 759 pdram_timing->tmod + pdram_timing->tzqinit; 760 mmio_write_32(CTL_REG(i, 9), tmp); 761 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 762 pdram_timing->tdllk << 16); 763 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 764 (pdram_timing->tmod << 24) | 765 (pdram_timing->tmrd << 16) | 766 (pdram_timing->trtp << 8)); 767 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 768 (pdram_timing->txsr - 769 pdram_timing->trcd) << 16); 770 } else if (timing_config->dram_type == LPDDR4) { 771 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 772 pdram_timing->tinit3); 773 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 774 (pdram_timing->tmrd << 24) | 775 (pdram_timing->tmrd << 16) | 776 (pdram_timing->trtp << 8)); 777 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 778 pdram_timing->txsr << 16); 779 } else { 780 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 781 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 782 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 783 (pdram_timing->tmrd << 24) | 784 (pdram_timing->tmrd << 16) | 785 (pdram_timing->trtp << 8)); 786 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 787 pdram_timing->txsr << 16); 788 } 789 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 790 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 791 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 792 ((pdram_timing->cl * 2) << 8)); 793 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 794 (pdram_timing->cwl << 16)); 795 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 796 pdram_timing->al << 24); 797 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 798 (pdram_timing->tras_min << 24) | 799 (pdram_timing->trc << 16) | 800 (pdram_timing->trrd << 8)); 801 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 802 (pdram_timing->tfaw << 16) | 803 (pdram_timing->trppb << 8) | 804 pdram_timing->twtr); 805 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 806 pdram_timing->tras_max); 807 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 808 max(1, pdram_timing->tckesr)); 809 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 810 (pdram_timing->trcd << 24)); 811 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 812 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 813 pdram_timing->tmrz << 24); 814 tmp = pdram_timing->tdal ? pdram_timing->tdal : 815 (pdram_timing->twr + pdram_timing->trp); 816 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 817 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 818 pdram_timing->trp << 8); 819 mmio_write_32(CTL_REG(i, 49), 820 ((pdram_timing->trefi - 8) << 16) | 821 pdram_timing->trfc); 822 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 823 pdram_timing->txp << 16); 824 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 825 pdram_timing->txpdll); 826 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 827 pdram_timing->tmrri << 8); 828 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 829 (pdram_timing->tckehcs << 16) | 830 (pdram_timing->tckelcs << 8) | 831 pdram_timing->tcscke); 832 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 833 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 834 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 835 (pdram_timing->tckehcmd << 24) | 836 (pdram_timing->tckelcmd << 16)); 837 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 838 (pdram_timing->tescke << 16) | 839 (pdram_timing->tsr << 8) | 840 pdram_timing->tckckel); 841 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 842 (pdram_timing->tcmdcke << 8) | 843 pdram_timing->tcsckeh); 844 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 845 (pdram_timing->tcksre << 24)); 846 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 847 pdram_timing->tcksrx); 848 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 849 (timing_config->dllbp << 25)); 850 mmio_write_32(CTL_REG(i, 125), 851 (pdram_timing->tvrcg_disable << 16) | 852 pdram_timing->tvrcg_enable); 853 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 854 (pdram_timing->tckfspe << 16) | 855 pdram_timing->tfc_long); 856 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 857 pdram_timing->tvref_long); 858 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 859 pdram_timing->mr[0] << 16); 860 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 861 pdram_timing->mr[1]); 862 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 863 pdram_timing->mr[3] << 16); 864 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 865 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 866 pdram_timing->mr[0] << 16); 867 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 868 pdram_timing->mr[1]); 869 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 870 pdram_timing->mr[3] << 16); 871 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 872 if (timing_config->dram_type == LPDDR4) { 873 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 874 pdram_timing->mr12); 875 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 876 pdram_timing->mr14); 877 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 878 pdram_timing->mr22); 879 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 880 pdram_timing->mr12); 881 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 882 pdram_timing->mr14); 883 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 884 pdram_timing->mr22); 885 } 886 mmio_write_32(CTL_REG(i, 182), 887 ((pdram_timing->tzqinit / 2) << 16) | 888 pdram_timing->tzqinit); 889 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 890 pdram_timing->tzqcs); 891 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 892 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 893 pdram_timing->tzqreset); 894 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 895 pdram_timing->todton << 16); 896 897 if (timing_config->odt) { 898 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 899 if (timing_config->freq < 400) 900 tmp = 4 << 24; 901 else 902 tmp = 8 << 24; 903 } else { 904 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 905 tmp = 2 << 24; 906 } 907 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 908 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 909 (pdram_timing->tdqsck_max << 24)); 910 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 911 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 912 (get_wrlat_adj(timing_config->dram_type, 913 pdram_timing->cwl) << 8) | 914 get_rdlat_adj(timing_config->dram_type, 915 pdram_timing->cl)); 916 917 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 918 (4 * pdram_timing->trefi) & 0xffff); 919 920 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 921 ((2 * pdram_timing->trefi) & 0xffff) << 16); 922 923 if ((timing_config->dram_type == LPDDR3) || 924 (timing_config->dram_type == LPDDR4)) { 925 tmp = get_pi_wrlat(pdram_timing, timing_config); 926 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 927 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 928 } else { 929 tmp = 0; 930 } 931 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 932 (tmp & 0x3f) << 24); 933 934 if ((timing_config->dram_type == LPDDR3) || 935 (timing_config->dram_type == LPDDR4)) { 936 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 937 tmp = pdram_timing->cl + 938 get_pi_todtoff_min(pdram_timing, timing_config); 939 tmp--; 940 /* todtoff_max */ 941 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 942 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 943 } else { 944 tmp = pdram_timing->cl - pdram_timing->cwl; 945 } 946 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 947 (tmp & 0x3f) << 16); 948 949 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 950 (get_pi_tdfi_phy_rdlat(pdram_timing, 951 timing_config) & 952 0xff) << 24); 953 954 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 955 ((2 * pdram_timing->trefi) & 0xffff) << 16); 956 957 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 958 (2 * pdram_timing->trefi) & 0xffff); 959 960 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 961 962 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 963 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 964 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 965 tmp1++; 966 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 967 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 968 969 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 970 tmp = tmp + 18; 971 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 972 973 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 974 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 975 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 976 if (tmp1 == 0) 977 tmp = 0; 978 else if (tmp1 < 5) 979 tmp = tmp1 - 1; 980 else 981 tmp = tmp1 - 5; 982 } else { 983 tmp = tmp1 - 2; 984 } 985 986 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 987 988 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 989 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 990 (pdram_timing->cl >= 5)) 991 tmp = pdram_timing->cl - 5; 992 else 993 tmp = pdram_timing->cl - 2; 994 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 995 } 996 } 997 998 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 999 { 1000 uint32_t i, tmp; 1001 1002 if (nmhz <= PHY_DLL_BYPASS_FREQ) 1003 tmp = 0; 1004 else 1005 tmp = 1; 1006 1007 for (i = 0; i < ch_cnt; i++) { 1008 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 1009 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 1010 } 1011 } 1012 1013 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1014 struct dram_timing_t *pdram_timing, 1015 uint32_t fn) 1016 { 1017 if (fn == 0) 1018 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1019 else 1020 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1021 } 1022 1023 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1024 struct dram_timing_t *pdram_timing) 1025 { 1026 uint32_t tmp, tmp1, tmp2; 1027 uint32_t i; 1028 1029 for (i = 0; i < timing_config->ch_cnt; i++) { 1030 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1031 tmp = 4 * pdram_timing->trefi; 1032 mmio_write_32(PI_REG(i, 2), tmp); 1033 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1034 tmp = 2 * pdram_timing->trefi; 1035 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1036 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1037 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1038 1039 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1040 if (timing_config->dram_type == LPDDR4) 1041 tmp = 2; 1042 else 1043 tmp = 0; 1044 tmp = (pdram_timing->bl / 2) + 4 + 1045 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1046 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1047 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1048 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1049 if (timing_config->dram_type == LPDDR3) { 1050 tmp = get_pi_wrlat(pdram_timing, timing_config); 1051 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1052 } 1053 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1054 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1055 PI_ADD_LATENCY << 8); 1056 1057 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1058 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1059 (pdram_timing->cl * 2) << 16); 1060 /* PI_46 PI_TREF_F0:RW:16:16 */ 1061 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1062 pdram_timing->trefi << 16); 1063 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1064 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1065 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1066 if (timing_config->dram_type == LPDDR3) { 1067 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1068 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1069 tmp << 24); 1070 } 1071 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1072 if ((timing_config->dram_type == LPDDR3) || 1073 (timing_config->dram_type == LPDDR4)) { 1074 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1075 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1076 if (tmp1 > tmp2) 1077 tmp = tmp1 - tmp2; 1078 else 1079 tmp = 0; 1080 } else if (timing_config->dram_type == DDR3) { 1081 tmp = 0; 1082 } 1083 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1084 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1085 if ((timing_config->dram_type == LPDDR3) || 1086 (timing_config->dram_type == LPDDR4)) { 1087 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1088 tmp1 = pdram_timing->cl; 1089 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1090 tmp1--; 1091 /* todtoff_max */ 1092 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1093 if (tmp1 > tmp2) 1094 tmp = tmp1 - tmp2; 1095 else 1096 tmp = 0; 1097 } else if (timing_config->dram_type == DDR3) { 1098 tmp = pdram_timing->cl - pdram_timing->cwl; 1099 } 1100 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1101 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1102 tmp = get_pi_rdlat_adj(pdram_timing); 1103 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1104 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1105 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1106 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1107 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1108 tmp1 = tmp; 1109 if (tmp1 == 0) 1110 tmp = 0; 1111 else if (tmp1 < 5) 1112 tmp = tmp1 - 1; 1113 else 1114 tmp = tmp1 - 5; 1115 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1116 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1117 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1118 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1119 tmp1++; 1120 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1121 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1122 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1123 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1124 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1125 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1126 pdram_timing->tmrz << 8); 1127 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1128 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1129 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1130 tmp1++; 1131 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1132 tmp = tmp1 + 5; 1133 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1134 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1135 tmp = 10000 / (1000000 / pdram_timing->mhz); 1136 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1137 tmp++; 1138 if (pdram_timing->mhz <= 100) 1139 tmp = tmp + 1; 1140 else 1141 tmp = tmp + 8; 1142 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1143 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1144 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1145 pdram_timing->mr[1] << 8); 1146 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1147 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1148 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1149 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1150 pdram_timing->mr[1] << 16); 1151 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1152 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1153 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1154 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1155 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1156 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1157 pdram_timing->mr[2] << 16); 1158 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1159 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1160 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1161 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1162 pdram_timing->mr[2] << 16); 1163 /* PI_156 PI_TFC_F0:RW:0:10 */ 1164 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); 1165 /* PI_158 PI_TWR_F0:RW:24:6 */ 1166 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1167 pdram_timing->twr << 24); 1168 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1169 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1170 pdram_timing->twtr << 16); 1171 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1172 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1173 pdram_timing->trcd << 8); 1174 /* PI_158 PI_TRP_F0:RW:0:8 */ 1175 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1176 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1177 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1178 pdram_timing->trtp << 24); 1179 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1180 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1181 pdram_timing->tras_min << 24); 1182 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1183 tmp = pdram_timing->tras_max * 99 / 100; 1184 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1185 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1186 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1187 pdram_timing->tmrd << 16); 1188 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1189 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1190 pdram_timing->tdqsck_max); 1191 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1192 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1193 (2 * pdram_timing->trefi) << 8); 1194 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1195 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1196 20 * pdram_timing->trefi); 1197 } 1198 } 1199 1200 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1201 struct dram_timing_t *pdram_timing) 1202 { 1203 uint32_t tmp, tmp1, tmp2; 1204 uint32_t i; 1205 1206 for (i = 0; i < timing_config->ch_cnt; i++) { 1207 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1208 tmp = 4 * pdram_timing->trefi; 1209 mmio_write_32(PI_REG(i, 4), tmp); 1210 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1211 tmp = 2 * pdram_timing->trefi; 1212 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1213 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1214 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1215 1216 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1217 if (timing_config->dram_type == LPDDR4) 1218 tmp = 2; 1219 else 1220 tmp = 0; 1221 tmp = (pdram_timing->bl / 2) + 4 + 1222 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1223 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1224 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1225 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1226 if (timing_config->dram_type == LPDDR3) { 1227 tmp = get_pi_wrlat(pdram_timing, timing_config); 1228 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1229 tmp << 24); 1230 } 1231 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1232 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1233 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1234 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1235 pdram_timing->cl * 2); 1236 /* PI_47 PI_TREF_F1:RW:16:16 */ 1237 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1238 pdram_timing->trefi << 16); 1239 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1240 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1241 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1242 if (timing_config->dram_type == LPDDR3) { 1243 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1244 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1245 } 1246 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1247 if ((timing_config->dram_type == LPDDR3) || 1248 (timing_config->dram_type == LPDDR4)) { 1249 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1250 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1251 if (tmp1 > tmp2) 1252 tmp = tmp1 - tmp2; 1253 else 1254 tmp = 0; 1255 } else if (timing_config->dram_type == DDR3) { 1256 tmp = 0; 1257 } 1258 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1259 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1260 if ((timing_config->dram_type == LPDDR3) || 1261 (timing_config->dram_type == LPDDR4)) { 1262 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1263 tmp1 = pdram_timing->cl + 1264 get_pi_todtoff_min(pdram_timing, timing_config); 1265 tmp1--; 1266 /* todtoff_max */ 1267 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1268 if (tmp1 > tmp2) 1269 tmp = tmp1 - tmp2; 1270 else 1271 tmp = 0; 1272 } else if (timing_config->dram_type == DDR3) 1273 tmp = pdram_timing->cl - pdram_timing->cwl; 1274 1275 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1276 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1277 tmp = get_pi_rdlat_adj(pdram_timing); 1278 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1279 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1280 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1281 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1282 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1283 tmp1 = tmp; 1284 if (tmp1 == 0) 1285 tmp = 0; 1286 else if (tmp1 < 5) 1287 tmp = tmp1 - 1; 1288 else 1289 tmp = tmp1 - 5; 1290 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1291 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1292 /* tadr=20ns */ 1293 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1294 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1295 tmp1++; 1296 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1297 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1298 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1299 tmp = tmp + 18; 1300 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1301 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1302 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1303 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1304 /* tds_train=ceil(2/ns) */ 1305 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1306 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1307 tmp1++; 1308 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1309 tmp = tmp1 + 5; 1310 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1311 tmp << 16); 1312 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1313 tmp = 10000 / (1000000 / pdram_timing->mhz); 1314 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1315 tmp++; 1316 if (pdram_timing->mhz <= 100) 1317 tmp = tmp + 1; 1318 else 1319 tmp = tmp + 8; 1320 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1321 tmp << 24); 1322 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1323 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1324 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1325 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1326 pdram_timing->mr[1] << 8); 1327 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1328 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1329 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1330 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1331 pdram_timing->mr[1] << 8); 1332 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1333 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1334 pdram_timing->mr[2] << 16); 1335 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1336 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1337 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1338 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1339 pdram_timing->mr[2] << 16); 1340 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1341 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1342 /* PI_156 PI_TFC_F1:RW:16:10 */ 1343 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1344 pdram_timing->trfc << 16); 1345 /* PI_162 PI_TWR_F1:RW:8:6 */ 1346 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1347 pdram_timing->twr << 8); 1348 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1349 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1350 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1351 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1352 pdram_timing->trcd << 24); 1353 /* PI_161 PI_TRP_F1:RW:16:8 */ 1354 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1355 pdram_timing->trp << 16); 1356 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1357 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1358 pdram_timing->trtp << 8); 1359 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1360 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1361 pdram_timing->tras_min << 24); 1362 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1363 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1364 pdram_timing->tras_max * 99 / 100); 1365 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1366 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1367 pdram_timing->tmrd << 16); 1368 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1369 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1370 pdram_timing->tdqsck_max); 1371 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1372 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1373 2 * pdram_timing->trefi); 1374 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1375 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1376 20 * pdram_timing->trefi); 1377 } 1378 } 1379 1380 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1381 struct dram_timing_t *pdram_timing, 1382 uint32_t fn) 1383 { 1384 if (fn == 0) 1385 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1386 else 1387 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1388 } 1389 1390 static void gen_rk3399_set_odt(uint32_t odt_en) 1391 { 1392 uint32_t drv_odt_val; 1393 uint32_t i; 1394 1395 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1396 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1397 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1398 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1399 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1400 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1401 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1402 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1403 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1404 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1405 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1406 } 1407 } 1408 1409 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1410 uint32_t index, uint32_t dram_type) 1411 { 1412 uint32_t sw_master_mode = 0; 1413 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1414 uint32_t i; 1415 1416 if (dram_type == DDR3) 1417 total_delay = PI_PAD_DELAY_PS_VALUE; 1418 else if (dram_type == LPDDR3) 1419 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1420 else 1421 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1422 /* total_delay + 0.55tck */ 1423 total_delay += (55 * 10000)/mhz; 1424 rddqs_latency = total_delay * mhz / 1000000; 1425 total_delay -= rddqs_latency * 1000000 / mhz; 1426 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1427 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1428 sw_master_mode = 0xc; 1429 mmio_setbits_32(PHY_REG(ch, 514), 1); 1430 mmio_setbits_32(PHY_REG(ch, 642), 1); 1431 mmio_setbits_32(PHY_REG(ch, 770), 1); 1432 1433 /* setting bypass mode slave delay */ 1434 for (i = 0; i < 4; i++) { 1435 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1436 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1437 0x4a0 << 8); 1438 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1439 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1440 0xa0); 1441 /* rd rddqs_gate delay */ 1442 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1443 rddqs_gate_delay); 1444 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1445 rddqs_latency); 1446 } 1447 for (i = 0; i < 3; i++) 1448 /* adr delay */ 1449 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1450 0x7ff << 16, 0x80 << 16); 1451 1452 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1453 /* 1454 * old status is normal mode, 1455 * and saving the wrdqs slave delay 1456 */ 1457 for (i = 0; i < 4; i++) { 1458 /* save and clear wr dqs slave delay */ 1459 wrdqs_delay_val[ch][index][i] = 0x3ff & 1460 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1461 >> 16); 1462 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1463 0x03ff << 16, 0 << 16); 1464 /* 1465 * in normal mode the cmd may delay 1cycle by 1466 * wrlvl and in bypass mode making dqs also 1467 * delay 1cycle. 1468 */ 1469 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1470 0x07 << 8, 0x1 << 8); 1471 } 1472 } 1473 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1474 /* old status is bypass mode and restore wrlvl resume */ 1475 for (i = 0; i < 4; i++) { 1476 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1477 0x03ff << 16, 1478 (wrdqs_delay_val[ch][index][i] & 1479 0x3ff) << 16); 1480 /* resume phy_write_path_lat_add */ 1481 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1482 } 1483 } 1484 1485 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1486 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1487 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1488 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1489 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1490 1491 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1492 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1493 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1494 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1495 } 1496 1497 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1498 struct drv_odt_lp_config *drv_config, 1499 struct dram_timing_t *pdram_timing, 1500 uint32_t fn) 1501 { 1502 uint32_t tmp, i, div, j; 1503 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1504 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1505 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1506 uint32_t extra_adder, delta, hs_offset; 1507 1508 for (i = 0; i < timing_config->ch_cnt; i++) { 1509 1510 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1511 ie_enable = PI_IE_ENABLE_VALUE; 1512 tsel_enable = PI_TSEL_ENABLE_VALUE; 1513 1514 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1515 1516 /* PHY_LOW_FREQ_SEL */ 1517 /* DENALI_PHY_913 1bit offset_0 */ 1518 if (timing_config->freq > 400) 1519 mmio_clrbits_32(PHY_REG(i, 913), 1); 1520 else 1521 mmio_setbits_32(PHY_REG(i, 913), 1); 1522 1523 /* PHY_RPTR_UPDATE_x */ 1524 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1525 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1526 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1527 tmp++; 1528 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1529 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1530 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1531 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1532 1533 /* PHY_PLL_CTRL */ 1534 /* DENALI_PHY_911 13bits offset_0 */ 1535 /* PHY_LP4_BOOT_PLL_CTRL */ 1536 /* DENALI_PHY_919 13bits offset_0 */ 1537 if (pdram_timing->mhz <= 150) 1538 tmp = 3; 1539 else if (pdram_timing->mhz <= 300) 1540 tmp = 2; 1541 else if (pdram_timing->mhz <= 600) 1542 tmp = 1; 1543 else 1544 tmp = 0; 1545 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1546 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1547 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1548 1549 /* PHY_PLL_CTRL_CA */ 1550 /* DENALI_PHY_911 13bits offset_16 */ 1551 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1552 /* DENALI_PHY_919 13bits offset_16 */ 1553 if (pdram_timing->mhz <= 150) 1554 tmp = 3; 1555 else if (pdram_timing->mhz <= 300) 1556 tmp = 2; 1557 else if (pdram_timing->mhz <= 600) 1558 tmp = 1; 1559 else 1560 tmp = 0; 1561 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1562 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1563 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1564 1565 /* PHY_TCKSRE_WAIT */ 1566 /* DENALI_PHY_922 4bits offset_24 */ 1567 if (pdram_timing->mhz <= 400) 1568 tmp = 1; 1569 else if (pdram_timing->mhz <= 800) 1570 tmp = 3; 1571 else if (pdram_timing->mhz <= 1000) 1572 tmp = 4; 1573 else 1574 tmp = 5; 1575 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1576 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1577 div = pdram_timing->mhz / (2 * 20); 1578 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1579 if (div < j) 1580 break; 1581 } 1582 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1583 mmio_setbits_32(PHY_REG(i, 927), (1 << 22)); 1584 1585 if (timing_config->dram_type == DDR3) { 1586 mem_delay_ps = 0; 1587 trpre_min_ps = 1000; 1588 } else if (timing_config->dram_type == LPDDR4) { 1589 mem_delay_ps = 1500; 1590 trpre_min_ps = 900; 1591 } else if (timing_config->dram_type == LPDDR3) { 1592 mem_delay_ps = 2500; 1593 trpre_min_ps = 900; 1594 } else { 1595 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1596 return; 1597 } 1598 total_delay_ps = mem_delay_ps + pad_delay_ps; 1599 delay_frac_ps = 1000 * total_delay_ps / 1600 (1000000 / pdram_timing->mhz); 1601 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1602 gate_delay_frac_ps = gate_delay_ps % 1000; 1603 tmp = gate_delay_frac_ps * 0x200 / 1000; 1604 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1605 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1606 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1607 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1608 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1609 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1610 1611 tmp = gate_delay_ps / 1000; 1612 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1613 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1614 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1615 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1616 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1617 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1618 /* PHY_GTLVL_LAT_ADJ_START */ 1619 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1620 tmp = delay_frac_ps / 1000; 1621 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1622 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1623 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1624 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1625 1626 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1627 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1628 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1629 rddata_en_ie_dly++; 1630 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1631 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1632 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1633 tsel_adder++; 1634 if (rddata_en_ie_dly > tsel_adder) 1635 extra_adder = rddata_en_ie_dly - tsel_adder; 1636 else 1637 extra_adder = 0; 1638 delta = cas_lat - rddata_en_ie_dly; 1639 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1640 hs_offset = 2; 1641 else 1642 hs_offset = 1; 1643 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1644 tmp = 0; 1645 else if ((delta == 2) || (delta == 1)) 1646 tmp = rddata_en_ie_dly - 0 - extra_adder; 1647 else 1648 tmp = extra_adder; 1649 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1650 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1651 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1652 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1653 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1654 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1655 /* PHY_RDDATA_EN_TSEL_DLY */ 1656 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1657 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1658 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1659 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1660 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1661 1662 if (tsel_adder > rddata_en_ie_dly) 1663 extra_adder = tsel_adder - rddata_en_ie_dly; 1664 else 1665 extra_adder = 0; 1666 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1667 tmp = tsel_adder; 1668 else 1669 tmp = rddata_en_ie_dly - 0 + extra_adder; 1670 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1671 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1672 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1673 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1674 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1675 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1676 /* PHY_RDDATA_EN_DLY */ 1677 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1678 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1679 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1680 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1681 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1682 1683 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1684 /* 1685 * Note:Per-CS Training is not compatible at speeds 1686 * under 533 MHz. If the PHY is running at a speed 1687 * less than 533MHz, all phy_per_cs_training_en_X 1688 * parameters must be cleared to 0. 1689 */ 1690 1691 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1692 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1693 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1694 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1695 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1696 } else { 1697 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1698 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1699 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1700 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1701 } 1702 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1703 timing_config->dram_type); 1704 } 1705 } 1706 1707 static int to_get_clk_index(unsigned int mhz) 1708 { 1709 int pll_cnt, i; 1710 1711 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1712 1713 /* Assumming rate_table is in descending order */ 1714 for (i = 0; i < pll_cnt; i++) { 1715 if (mhz >= dpll_rates_table[i].mhz) 1716 break; 1717 } 1718 1719 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1720 if (i == pll_cnt) 1721 i = pll_cnt - 1; 1722 1723 return i; 1724 } 1725 1726 uint32_t ddr_get_rate(void) 1727 { 1728 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1729 1730 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1731 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1732 postdiv1 = 1733 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1734 postdiv2 = 1735 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1736 1737 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1738 } 1739 1740 /* 1741 * return: bit12: channel 1, external self-refresh 1742 * bit11: channel 1, stdby_mode 1743 * bit10: channel 1, self-refresh with controller and memory clock gate 1744 * bit9: channel 1, self-refresh 1745 * bit8: channel 1, power-down 1746 * 1747 * bit4: channel 1, external self-refresh 1748 * bit3: channel 0, stdby_mode 1749 * bit2: channel 0, self-refresh with controller and memory clock gate 1750 * bit1: channel 0, self-refresh 1751 * bit0: channel 0, power-down 1752 */ 1753 uint32_t exit_low_power(void) 1754 { 1755 uint32_t low_power = 0; 1756 uint32_t channel_mask; 1757 uint32_t tmp, i; 1758 1759 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1760 0x3; 1761 for (i = 0; i < 2; i++) { 1762 if (!(channel_mask & (1 << i))) 1763 continue; 1764 1765 /* exit stdby mode */ 1766 mmio_write_32(CIC_BASE + CIC_CTRL1, 1767 (1 << (i + 16)) | (0 << i)); 1768 /* exit external self-refresh */ 1769 tmp = i ? 12 : 8; 1770 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1771 0x1) << (4 + 8 * i); 1772 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1773 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1774 ; 1775 /* exit auto low-power */ 1776 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1777 /* lp_cmd to exit */ 1778 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1779 0x40) { 1780 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1781 ; 1782 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1783 0x69 << 24); 1784 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1785 0x40) 1786 ; 1787 } 1788 } 1789 return low_power; 1790 } 1791 1792 void resume_low_power(uint32_t low_power) 1793 { 1794 uint32_t channel_mask; 1795 uint32_t tmp, i, val; 1796 1797 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1798 0x3; 1799 for (i = 0; i < 2; i++) { 1800 if (!(channel_mask & (1 << i))) 1801 continue; 1802 1803 /* resume external self-refresh */ 1804 tmp = i ? 12 : 8; 1805 val = (low_power >> (4 + 8 * i)) & 0x1; 1806 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1807 /* resume auto low-power */ 1808 val = (low_power >> (8 * i)) & 0x7; 1809 mmio_setbits_32(CTL_REG(i, 101), val); 1810 /* resume stdby mode */ 1811 val = (low_power >> (3 + 8 * i)) & 0x1; 1812 mmio_write_32(CIC_BASE + CIC_CTRL1, 1813 (1 << (i + 16)) | (val << i)); 1814 } 1815 } 1816 1817 static void dram_low_power_config(void) 1818 { 1819 uint32_t tmp, i; 1820 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1821 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1822 1823 if (dram_type == DDR3) 1824 tmp = (2 << 16) | (0x7 << 8); 1825 else 1826 tmp = (3 << 16) | (0x7 << 8); 1827 1828 for (i = 0; i < ch_cnt; i++) 1829 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1830 1831 /* standby idle */ 1832 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1833 1834 if (ch_cnt == 2) { 1835 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1836 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1837 (0x1<<7)) << 16) | 1838 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1839 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1840 } 1841 1842 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1843 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1844 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1845 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1846 } 1847 1848 void dram_dfs_init(void) 1849 { 1850 uint32_t trefi0, trefi1; 1851 1852 /* get sdram config for os reg */ 1853 get_dram_drv_odt_val(sdram_config.dramtype, 1854 &rk3399_dram_status.drv_odt_lp_cfg); 1855 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1856 &sdram_config, 1857 &rk3399_dram_status.drv_odt_lp_cfg); 1858 1859 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1860 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1861 1862 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1863 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1864 rk3399_dram_status.current_index = 1865 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1866 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1867 rk3399_dram_status.index_freq[0] /= 2; 1868 rk3399_dram_status.index_freq[1] /= 2; 1869 } 1870 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) 1871 & 0x1] = 0; 1872 /* 1873 * following register decide if NOC stall the access request 1874 * or return error when NOC being idled. when doing ddr frequency 1875 * scaling in M0 or DCF, we need to make sure noc stall the access 1876 * request, if return error cpu may data abort when ddr frequency 1877 * changing. it don't need to set this register every times, 1878 * so we init this register in function dram_dfs_init(). 1879 */ 1880 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1881 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1882 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1883 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1884 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1885 1886 dram_low_power_config(); 1887 } 1888 1889 /* 1890 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1891 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1892 * arg2: bit0: if odt en 1893 */ 1894 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1895 { 1896 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1897 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1898 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1899 1900 dram_type = rk3399_dram_status.timing_config.dram_type; 1901 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1902 1903 lp_cfg->sr_idle = arg0 & 0xff; 1904 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1905 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1906 lp_cfg->pd_idle = arg1 & 0xfff; 1907 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1908 1909 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1910 1911 exit_low_power(); 1912 1913 *low_power = 0; 1914 1915 /* pd_idle en */ 1916 if (lp_cfg->pd_idle) 1917 *low_power |= ((1 << 0) | (1 << 8)); 1918 /* sr_idle en srpd_lite_idle */ 1919 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1920 *low_power |= ((1 << 1) | (1 << 9)); 1921 /* sr_mc_gate_idle */ 1922 if (lp_cfg->sr_mc_gate_idle) 1923 *low_power |= ((1 << 2) | (1 << 10)); 1924 /* standbyidle */ 1925 if (lp_cfg->standby_idle) { 1926 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1927 *low_power |= ((1 << 3) | (1 << 11)); 1928 else 1929 *low_power |= (1 << 3); 1930 } 1931 1932 pd_tmp = arg1; 1933 if (dram_type != LPDDR4) 1934 pd_tmp = arg1 & 0xfff; 1935 sr_tmp = arg0 & 0xffff; 1936 for (i = 0; i < ch_count; i++) { 1937 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1938 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1939 } 1940 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1941 1942 return 0; 1943 } 1944 1945 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1946 { 1947 /* set PARAM to M0_FUNC_DRAM */ 1948 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); 1949 1950 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1951 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1952 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1953 REFDIV(pll_div.refdiv)); 1954 1955 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1956 1957 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1958 } 1959 1960 static uint32_t prepare_ddr_timing(uint32_t mhz) 1961 { 1962 uint32_t index; 1963 struct dram_timing_t dram_timing; 1964 1965 rk3399_dram_status.timing_config.freq = mhz; 1966 1967 if (mhz < 300) 1968 rk3399_dram_status.timing_config.dllbp = 1; 1969 else 1970 rk3399_dram_status.timing_config.dllbp = 0; 1971 1972 if (rk3399_dram_status.timing_config.odt == 1) 1973 gen_rk3399_set_odt(1); 1974 1975 index = (rk3399_dram_status.current_index + 1) & 0x1; 1976 if (rk3399_dram_status.index_freq[index] == mhz) 1977 goto out; 1978 1979 /* 1980 * checking if having available gate traiing timing for 1981 * target freq. 1982 */ 1983 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 1984 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 1985 &dram_timing, index); 1986 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 1987 &dram_timing, index); 1988 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 1989 &rk3399_dram_status.drv_odt_lp_cfg, 1990 &dram_timing, index); 1991 rk3399_dram_status.index_freq[index] = mhz; 1992 1993 out: 1994 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 1995 mhz); 1996 return index; 1997 } 1998 1999 void print_dram_status_info(void) 2000 { 2001 uint32_t *p; 2002 uint32_t i; 2003 2004 p = (uint32_t *) &rk3399_dram_status.timing_config; 2005 INFO("rk3399_dram_status.timing_config:\n"); 2006 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2007 tf_printf("%u\n", p[i]); 2008 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2009 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2010 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2011 tf_printf("%u\n", p[i]); 2012 } 2013 2014 uint32_t ddr_set_rate(uint32_t hz) 2015 { 2016 uint32_t low_power, index, ddr_index; 2017 uint32_t mhz = hz / (1000 * 1000); 2018 2019 if (mhz == 2020 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2021 goto out; 2022 2023 index = to_get_clk_index(mhz); 2024 mhz = dpll_rates_table[index].mhz; 2025 2026 ddr_index = prepare_ddr_timing(mhz); 2027 if (ddr_index > 1) 2028 goto out; 2029 2030 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2031 m0_start(); 2032 m0_wait_done(); 2033 m0_stop(); 2034 2035 if (rk3399_dram_status.timing_config.odt == 0) 2036 gen_rk3399_set_odt(0); 2037 2038 rk3399_dram_status.current_index = ddr_index; 2039 low_power = rk3399_dram_status.low_power_stat; 2040 resume_low_power(low_power); 2041 out: 2042 return mhz; 2043 } 2044 2045 uint32_t ddr_round_rate(uint32_t hz) 2046 { 2047 int index; 2048 uint32_t mhz = hz / (1000 * 1000); 2049 2050 index = to_get_clk_index(mhz); 2051 2052 return dpll_rates_table[index].mhz * 1000 * 1000; 2053 } 2054