1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_def.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <debug.h> 37 #include <desc_image_load.h> 38 #include <plat_arm.h> 39 #include <platform_def.h> 40 #include <string.h> 41 42 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 43 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 44 45 /* Weak definitions may be overridden in specific ARM standard platform */ 46 #pragma weak bl2_early_platform_setup 47 #pragma weak bl2_platform_setup 48 #pragma weak bl2_plat_arch_setup 49 #pragma weak bl2_plat_sec_mem_layout 50 51 #if LOAD_IMAGE_V2 52 53 #pragma weak bl2_plat_handle_post_image_load 54 55 #else /* LOAD_IMAGE_V2 */ 56 57 /******************************************************************************* 58 * This structure represents the superset of information that is passed to 59 * BL31, e.g. while passing control to it from BL2, bl31_params 60 * and other platform specific params 61 ******************************************************************************/ 62 typedef struct bl2_to_bl31_params_mem { 63 bl31_params_t bl31_params; 64 image_info_t bl31_image_info; 65 image_info_t bl32_image_info; 66 image_info_t bl33_image_info; 67 entry_point_info_t bl33_ep_info; 68 entry_point_info_t bl32_ep_info; 69 entry_point_info_t bl31_ep_info; 70 } bl2_to_bl31_params_mem_t; 71 72 73 static bl2_to_bl31_params_mem_t bl31_params_mem; 74 75 76 /* Weak definitions may be overridden in specific ARM standard platform */ 77 #pragma weak bl2_plat_get_bl31_params 78 #pragma weak bl2_plat_get_bl31_ep_info 79 #pragma weak bl2_plat_flush_bl31_params 80 #pragma weak bl2_plat_set_bl31_ep_info 81 #pragma weak bl2_plat_get_scp_bl2_meminfo 82 #pragma weak bl2_plat_get_bl32_meminfo 83 #pragma weak bl2_plat_set_bl32_ep_info 84 #pragma weak bl2_plat_get_bl33_meminfo 85 #pragma weak bl2_plat_set_bl33_ep_info 86 87 #if ARM_BL31_IN_DRAM 88 meminfo_t *bl2_plat_sec_mem_layout(void) 89 { 90 static meminfo_t bl2_dram_layout 91 __aligned(CACHE_WRITEBACK_GRANULE) = { 92 .total_base = BL31_BASE, 93 .total_size = (ARM_AP_TZC_DRAM1_BASE + 94 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 95 .free_base = BL31_BASE, 96 .free_size = (ARM_AP_TZC_DRAM1_BASE + 97 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 98 }; 99 100 return &bl2_dram_layout; 101 } 102 #else 103 meminfo_t *bl2_plat_sec_mem_layout(void) 104 { 105 return &bl2_tzram_layout; 106 } 107 #endif /* ARM_BL31_IN_DRAM */ 108 109 /******************************************************************************* 110 * This function assigns a pointer to the memory that the platform has kept 111 * aside to pass platform specific and trusted firmware related information 112 * to BL31. This memory is allocated by allocating memory to 113 * bl2_to_bl31_params_mem_t structure which is a superset of all the 114 * structure whose information is passed to BL31 115 * NOTE: This function should be called only once and should be done 116 * before generating params to BL31 117 ******************************************************************************/ 118 bl31_params_t *bl2_plat_get_bl31_params(void) 119 { 120 bl31_params_t *bl2_to_bl31_params; 121 122 /* 123 * Initialise the memory for all the arguments that needs to 124 * be passed to BL31 125 */ 126 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 127 128 /* Assign memory for TF related information */ 129 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 130 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 131 132 /* Fill BL31 related information */ 133 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 134 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 135 VERSION_1, 0); 136 137 /* Fill BL32 related information if it exists */ 138 #ifdef BL32_BASE 139 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 140 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 141 VERSION_1, 0); 142 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 143 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 144 VERSION_1, 0); 145 #endif /* BL32_BASE */ 146 147 /* Fill BL33 related information */ 148 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 149 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 150 PARAM_EP, VERSION_1, 0); 151 152 /* BL33 expects to receive the primary CPU MPID (through x0) */ 153 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 154 155 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 156 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 157 VERSION_1, 0); 158 159 return bl2_to_bl31_params; 160 } 161 162 /* Flush the TF params and the TF plat params */ 163 void bl2_plat_flush_bl31_params(void) 164 { 165 flush_dcache_range((unsigned long)&bl31_params_mem, 166 sizeof(bl2_to_bl31_params_mem_t)); 167 } 168 169 /******************************************************************************* 170 * This function returns a pointer to the shared memory that the platform 171 * has kept to point to entry point information of BL31 to BL2 172 ******************************************************************************/ 173 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 174 { 175 #if DEBUG 176 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; 177 #endif 178 179 return &bl31_params_mem.bl31_ep_info; 180 } 181 #endif /* LOAD_IMAGE_V2 */ 182 183 /******************************************************************************* 184 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 185 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 186 * Copy it to a safe location before its reclaimed by later BL2 functionality. 187 ******************************************************************************/ 188 void arm_bl2_early_platform_setup(meminfo_t *mem_layout) 189 { 190 /* Initialize the console to provide early debug support */ 191 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 192 ARM_CONSOLE_BAUDRATE); 193 194 /* Setup the BL2 memory layout */ 195 bl2_tzram_layout = *mem_layout; 196 197 /* Initialise the IO layer and register platform IO devices */ 198 plat_arm_io_setup(); 199 } 200 201 void bl2_early_platform_setup(meminfo_t *mem_layout) 202 { 203 arm_bl2_early_platform_setup(mem_layout); 204 } 205 206 /* 207 * Perform ARM standard platform setup. 208 */ 209 void arm_bl2_platform_setup(void) 210 { 211 /* Initialize the secure environment */ 212 plat_arm_security_setup(); 213 } 214 215 void bl2_platform_setup(void) 216 { 217 arm_bl2_platform_setup(); 218 } 219 220 /******************************************************************************* 221 * Perform the very early platform specific architectural setup here. At the 222 * moment this is only initializes the mmu in a quick and dirty way. 223 ******************************************************************************/ 224 void arm_bl2_plat_arch_setup(void) 225 { 226 arm_setup_page_tables(bl2_tzram_layout.total_base, 227 bl2_tzram_layout.total_size, 228 BL_CODE_BASE, 229 BL_CODE_END, 230 BL_RO_DATA_BASE, 231 BL_RO_DATA_END 232 #if USE_COHERENT_MEM 233 , BL_COHERENT_RAM_BASE, 234 BL_COHERENT_RAM_END 235 #endif 236 ); 237 238 #ifdef AARCH32 239 enable_mmu_secure(0); 240 #else 241 enable_mmu_el1(0); 242 #endif 243 } 244 245 void bl2_plat_arch_setup(void) 246 { 247 arm_bl2_plat_arch_setup(); 248 } 249 250 #if LOAD_IMAGE_V2 251 /******************************************************************************* 252 * This function can be used by the platforms to update/use image 253 * information for given `image_id`. 254 ******************************************************************************/ 255 int bl2_plat_handle_post_image_load(unsigned int image_id) 256 { 257 int err = 0; 258 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 259 assert(bl_mem_params); 260 261 switch (image_id) { 262 #ifdef AARCH64 263 case BL32_IMAGE_ID: 264 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 265 break; 266 #endif 267 268 case BL33_IMAGE_ID: 269 /* BL33 expects to receive the primary CPU MPID (through r0) */ 270 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 271 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 272 break; 273 274 #ifdef SCP_BL2_BASE 275 case SCP_BL2_IMAGE_ID: 276 /* The subsequent handling of SCP_BL2 is platform specific */ 277 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 278 if (err) { 279 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 280 } 281 break; 282 #endif 283 } 284 285 return err; 286 } 287 288 #else /* LOAD_IMAGE_V2 */ 289 290 /******************************************************************************* 291 * Populate the extents of memory available for loading SCP_BL2 (if used), 292 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 293 ******************************************************************************/ 294 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 295 { 296 *scp_bl2_meminfo = bl2_tzram_layout; 297 } 298 299 /******************************************************************************* 300 * Before calling this function BL31 is loaded in memory and its entrypoint 301 * is set by load_image. This is a placeholder for the platform to change 302 * the entrypoint of BL31 and set SPSR and security state. 303 * On ARM standard platforms we only set the security state of the entrypoint 304 ******************************************************************************/ 305 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 306 entry_point_info_t *bl31_ep_info) 307 { 308 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 309 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 310 DISABLE_ALL_EXCEPTIONS); 311 } 312 313 314 /******************************************************************************* 315 * Before calling this function BL32 is loaded in memory and its entrypoint 316 * is set by load_image. This is a placeholder for the platform to change 317 * the entrypoint of BL32 and set SPSR and security state. 318 * On ARM standard platforms we only set the security state of the entrypoint 319 ******************************************************************************/ 320 #ifdef BL32_BASE 321 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 322 entry_point_info_t *bl32_ep_info) 323 { 324 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 325 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 326 } 327 328 /******************************************************************************* 329 * Populate the extents of memory available for loading BL32 330 ******************************************************************************/ 331 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 332 { 333 /* 334 * Populate the extents of memory available for loading BL32. 335 */ 336 bl32_meminfo->total_base = BL32_BASE; 337 bl32_meminfo->free_base = BL32_BASE; 338 bl32_meminfo->total_size = 339 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 340 bl32_meminfo->free_size = 341 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 342 } 343 #endif /* BL32_BASE */ 344 345 /******************************************************************************* 346 * Before calling this function BL33 is loaded in memory and its entrypoint 347 * is set by load_image. This is a placeholder for the platform to change 348 * the entrypoint of BL33 and set SPSR and security state. 349 * On ARM standard platforms we only set the security state of the entrypoint 350 ******************************************************************************/ 351 void bl2_plat_set_bl33_ep_info(image_info_t *image, 352 entry_point_info_t *bl33_ep_info) 353 { 354 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 355 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 356 } 357 358 /******************************************************************************* 359 * Populate the extents of memory available for loading BL33 360 ******************************************************************************/ 361 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 362 { 363 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 364 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 365 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 366 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 367 } 368 369 #endif /* LOAD_IMAGE_V2 */ 370