1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_PRIVATE_H__ 8 #define __PLAT_PRIVATE_H__ 9 10 #ifndef __ASSEMBLY__ 11 #include <mmio.h> 12 #include <stdint.h> 13 #include <xlat_tables.h> 14 #include <psci.h> 15 16 #define __sramdata __attribute__((section(".sram.data"))) 17 #define __sramconst __attribute__((section(".sram.rodata"))) 18 #define __sramfunc __attribute__((section(".sram.text"))) 19 20 #define __pmusramdata __attribute__((section(".pmusram.data"))) 21 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 22 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 23 24 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 25 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 26 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 27 extern uint32_t __sram_incbin_start, __sram_incbin_end; 28 29 30 /****************************************************************************** 31 * The register have write-mask bits, it is mean, if you want to set the bits, 32 * you needs set the write-mask bits at the same time, 33 * The write-mask bits is in high 16-bits. 34 * The fllowing macro definition helps access write-mask bits reg efficient! 35 ******************************************************************************/ 36 #define REG_MSK_SHIFT 16 37 38 #ifndef WMSK_BIT 39 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 40 #endif 41 42 /* set one bit with write mask */ 43 #ifndef BIT_WITH_WMSK 44 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 45 #endif 46 47 #ifndef BITS_SHIFT 48 #define BITS_SHIFT(bits, shift) (bits << (shift)) 49 #endif 50 51 #ifndef BITS_WITH_WMASK 52 #define BITS_WITH_WMASK(bits, msk, shift)\ 53 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 54 #endif 55 56 /****************************************************************************** 57 * Function and variable prototypes 58 *****************************************************************************/ 59 void plat_configure_mmu_el3(unsigned long total_base, 60 unsigned long total_size, 61 unsigned long, 62 unsigned long, 63 unsigned long, 64 unsigned long); 65 66 void plat_cci_init(void); 67 void plat_cci_enable(void); 68 void plat_cci_disable(void); 69 70 void plat_delay_timer_init(void); 71 72 void params_early_setup(void *plat_params_from_bl2); 73 74 void plat_rockchip_gic_driver_init(void); 75 void plat_rockchip_gic_init(void); 76 void plat_rockchip_gic_cpuif_enable(void); 77 void plat_rockchip_gic_cpuif_disable(void); 78 void plat_rockchip_gic_pcpu_init(void); 79 80 void plat_rockchip_pmu_init(void); 81 void plat_rockchip_soc_init(void); 82 uintptr_t plat_get_sec_entrypoint(void); 83 84 void platform_cpu_warmboot(void); 85 86 struct gpio_info *plat_get_rockchip_gpio_reset(void); 87 struct gpio_info *plat_get_rockchip_gpio_poweroff(void); 88 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 89 struct apio_info *plat_get_rockchip_suspend_apio(void); 90 void plat_rockchip_gpio_init(void); 91 92 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 93 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 94 plat_local_state_t lvl_state); 95 int rockchip_soc_cores_pwr_dm_off(void); 96 int rockchip_soc_sys_pwr_dm_suspend(void); 97 int rockchip_soc_cores_pwr_dm_suspend(void); 98 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 99 plat_local_state_t lvl_state); 100 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 101 plat_local_state_t lvl_state); 102 int rockchip_soc_cores_pwr_dm_on_finish(void); 103 int rockchip_soc_sys_pwr_dm_resume(void); 104 105 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 106 plat_local_state_t lvl_state); 107 int rockchip_soc_cores_pwr_dm_resume(void); 108 void __dead2 rockchip_soc_soft_reset(void); 109 void __dead2 rockchip_soc_system_off(void); 110 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 111 const psci_power_state_t *target_state); 112 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 113 114 extern const unsigned char rockchip_power_domain_tree_desc[]; 115 116 extern void *pmu_cpuson_entrypoint; 117 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 118 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 119 120 extern const mmap_region_t plat_rk_mmap[]; 121 122 void rockchip_plat_mmu_el3(void); 123 124 #endif /* __ASSEMBLY__ */ 125 126 /****************************************************************************** 127 * cpu up status 128 * The bits of macro value is not more than 12 bits for cmp instruction! 129 ******************************************************************************/ 130 #define PMU_CPU_HOTPLUG 0xf00 131 #define PMU_CPU_AUTO_PWRDN 0xf0 132 #define PMU_CLST_RET 0xa5 133 134 #endif /* __PLAT_PRIVATE_H__ */ 135