1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <dfs.h> 36 #include <dram.h> 37 #include <mmio.h> 38 #include <m0_ctl.h> 39 #include <platform_def.h> 40 #include <plat_private.h> 41 #include <rk3399_def.h> 42 #include <soc.h> 43 44 /* Table of regions to map using the MMU. */ 45 const mmap_region_t plat_rk_mmap[] = { 46 MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 49 MT_MEMORY | MT_RW | MT_SECURE), 50 51 { 0 } 52 }; 53 54 /* The RockChip power domain tree descriptor */ 55 const unsigned char rockchip_power_domain_tree_desc[] = { 56 /* No of root nodes */ 57 PLATFORM_SYSTEM_COUNT, 58 /* No of children for the root node */ 59 PLATFORM_CLUSTER_COUNT, 60 /* No of children for the first cluster node */ 61 PLATFORM_CLUSTER0_CORE_COUNT, 62 /* No of children for the second cluster node */ 63 PLATFORM_CLUSTER1_CORE_COUNT 64 }; 65 66 void secure_timer_init(void) 67 { 68 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); 69 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); 70 71 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 72 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); 73 74 /* auto reload & enable the timer */ 75 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 76 TIMER_EN | TIMER_FMODE); 77 } 78 79 void sgrf_init(void) 80 { 81 /* security config for master */ 82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), 83 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), 85 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 86 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), 87 SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); 88 89 /* security config for slave */ 90 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), 91 SGRF_PMU_SLV_S_CFGED | 92 SGRF_PMU_SLV_CRYPTO1_NS); 93 mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), 94 SGRF_PMU_SLV_CON1_CFG); 95 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), 96 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 97 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), 98 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 99 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), 100 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 101 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), 102 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 103 mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), 104 SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); 105 } 106 107 static void dma_secure_cfg(uint32_t secure) 108 { 109 if (secure) { 110 /* rgn0 secure for dmac0 and dmac1 */ 111 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 112 SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ 113 SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ 114 ); 115 116 /* set dmac0 boot, under secure state */ 117 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 118 SGRF_DMAC_CFG_S); 119 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 120 SGRF_DMAC_CFG_S); 121 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 122 SGRF_DMAC_CFG_S); 123 124 /* dmac0 soft reset */ 125 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 126 CRU_DMAC0_RST); 127 udelay(5); 128 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 129 CRU_DMAC0_RST_RLS); 130 131 /* set dmac1 boot, under secure state */ 132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 133 SGRF_DMAC_CFG_S); 134 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 135 SGRF_DMAC_CFG_S); 136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 137 SGRF_DMAC_CFG_S); 138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 139 SGRF_DMAC_CFG_S); 140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 141 SGRF_DMAC_CFG_S); 142 143 /* dmac1 soft reset */ 144 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 145 CRU_DMAC1_RST); 146 udelay(5); 147 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 148 CRU_DMAC1_RST_RLS); 149 } else { 150 /* rgn non-secure for dmac0 and dmac1 */ 151 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), 152 DMAC1_RGN_NS | DMAC0_RGN_NS); 153 154 /* set dmac0 boot, under non-secure state */ 155 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), 156 DMAC0_BOOT_CFG_NS); 157 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), 158 DMAC0_BOOT_PERIPH_NS); 159 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), 160 DMAC0_BOOT_ADDR_NS); 161 162 /* dmac0 soft reset */ 163 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 164 CRU_DMAC0_RST); 165 udelay(5); 166 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 167 CRU_DMAC0_RST_RLS); 168 169 /* set dmac1 boot, under non-secure state */ 170 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), 171 DMAC1_BOOT_CFG_NS); 172 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), 173 DMAC1_BOOT_PERIPH_L_NS); 174 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), 175 DMAC1_BOOT_ADDR_NS); 176 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), 177 DMAC1_BOOT_PERIPH_H_NS); 178 mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), 179 DMAC1_BOOT_IRQ_NS); 180 181 /* dmac1 soft reset */ 182 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 183 CRU_DMAC1_RST); 184 udelay(5); 185 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 186 CRU_DMAC1_RST_RLS); 187 } 188 } 189 190 /* pll suspend */ 191 struct deepsleep_data_s slp_data; 192 193 void secure_watchdog_disable(void) 194 { 195 slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3)); 196 197 /* disable CA53 wdt pclk */ 198 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 199 BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK, 200 PCLK_WDT_CA53_GATE_SHIFT)); 201 /* disable CM0 wdt pclk */ 202 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 203 BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK, 204 PCLK_WDT_CM0_GATE_SHIFT)); 205 } 206 207 void secure_watchdog_restore(void) 208 { 209 mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3), 210 slp_data.sgrf_con[3] | 211 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | 212 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); 213 } 214 215 static void sgrf_ddr_rgn_global_bypass(uint32_t bypass) 216 { 217 if (bypass) 218 /* set bypass (non-secure regions) for whole ddr regions */ 219 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 220 SGRF_DDR_RGN_BYPS); 221 else 222 /* cancel bypass for whole ddr regions */ 223 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 224 SGRF_DDR_RGN_NO_BYPS); 225 } 226 227 /** 228 * There are 8 + 1 regions for DDR secure control: 229 * DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB 230 * DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7 231 * 232 * DDR_RGN_0 - start address of the RGN0 233 * DDR_RGN_8 - end address of the RGN0 234 * DDR_RGN_1 - start address of the RGN1 235 * DDR_RGN_9 - end address of the RGN1 236 * ... 237 * DDR_RGN_7 - start address of the RGN7 238 * DDR_RGN_15 - end address of the RGN7 239 * DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable 240 * bit 8 is setting for RGNx, the rest of the memory and region 241 * which excludes RGN0~7, 0: disable, 1: enable 242 * bit 9, the global secure configuration via bypass, 0: disable 243 * bypass, 1: enable bypass 244 * 245 * @rgn - the DDR regions 0 ~ 7 which are can be configured. 246 * The @st_mb and @ed_mb indicate the start and end addresses for which to set 247 * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the 248 * address range 0x0 ~ 0xfffff is secure. 249 * 250 * For example, if we would like to set the range [0, 32MB) is security via 251 * DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31. 252 */ 253 static void sgrf_ddr_rgn_config(uint32_t rgn, 254 uintptr_t st, uintptr_t ed) 255 { 256 uintptr_t st_mb, ed_mb; 257 258 assert(rgn <= 7); 259 assert(st < ed); 260 261 /* check aligned 1MB */ 262 assert(st % SIZE_M(1) == 0); 263 assert(ed % SIZE_M(1) == 0); 264 265 st_mb = st / SIZE_M(1); 266 ed_mb = ed / SIZE_M(1); 267 268 /* set ddr region addr start */ 269 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), 270 BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0)); 271 272 /* set ddr region addr end */ 273 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), 274 BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0)); 275 276 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), 277 BIT_WITH_WMSK(rgn)); 278 } 279 280 static void secure_sgrf_ddr_rgn_init(void) 281 { 282 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); 283 sgrf_ddr_rgn_global_bypass(0); 284 } 285 286 static void set_pll_slow_mode(uint32_t pll_id) 287 { 288 if (pll_id == PPLL_ID) 289 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); 290 else 291 mmio_write_32((CRU_BASE + 292 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 293 } 294 295 static void set_pll_normal_mode(uint32_t pll_id) 296 { 297 if (pll_id == PPLL_ID) 298 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); 299 else 300 mmio_write_32(CRU_BASE + 301 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); 302 } 303 304 static void set_pll_bypass(uint32_t pll_id) 305 { 306 if (pll_id == PPLL_ID) 307 mmio_write_32(PMUCRU_BASE + 308 PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); 309 else 310 mmio_write_32(CRU_BASE + 311 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); 312 } 313 314 static void _pll_suspend(uint32_t pll_id) 315 { 316 set_pll_slow_mode(pll_id); 317 set_pll_bypass(pll_id); 318 } 319 320 /** 321 * disable_dvfs_plls - To suspend the specific PLLs 322 * 323 * When we close the center logic, the DPLL will be closed, 324 * so we need to keep the ABPLL and switch to it to supply 325 * clock for DDR during suspend, then we should not close 326 * the ABPLL and exclude ABPLL_ID. 327 */ 328 void disable_dvfs_plls(void) 329 { 330 _pll_suspend(CPLL_ID); 331 _pll_suspend(NPLL_ID); 332 _pll_suspend(VPLL_ID); 333 _pll_suspend(GPLL_ID); 334 _pll_suspend(ALPLL_ID); 335 } 336 337 /** 338 * disable_nodvfs_plls - To suspend the PPLL 339 */ 340 void disable_nodvfs_plls(void) 341 { 342 _pll_suspend(PPLL_ID); 343 } 344 345 /** 346 * restore_pll - Copy PLL settings from memory to a PLL. 347 * 348 * This will copy PLL settings from an array in memory to the memory mapped 349 * registers for a PLL. 350 * 351 * Note that: above the PLL exclude PPLL. 352 * 353 * pll_id: One of the values from enum plls_id 354 * src: Pointer to the array of values to restore from 355 */ 356 static void restore_pll(int pll_id, uint32_t *src) 357 { 358 /* Nice to have PLL off while configuring */ 359 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); 360 361 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); 362 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); 363 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); 364 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); 365 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); 366 367 /* Do PLL_CON3 since that will enable things */ 368 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); 369 370 /* Wait for PLL lock done */ 371 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & 372 0x80000000) == 0x0) 373 ; 374 } 375 376 /** 377 * save_pll - Copy PLL settings a PLL to memory 378 * 379 * This will copy PLL settings from the memory mapped registers for a PLL to 380 * an array in memory. 381 * 382 * Note that: above the PLL exclude PPLL. 383 * 384 * pll_id: One of the values from enum plls_id 385 * src: Pointer to the array of values to save to. 386 */ 387 static void save_pll(uint32_t *dst, int pll_id) 388 { 389 int i; 390 391 for (i = 0; i < PLL_CON_COUNT; i++) 392 dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); 393 } 394 395 /** 396 * prepare_abpll_for_ddrctrl - Copy DPLL settings to ABPLL 397 * 398 * This will copy DPLL settings from the memory mapped registers for a PLL to 399 * an array in memory. 400 */ 401 void prepare_abpll_for_ddrctrl(void) 402 { 403 save_pll(slp_data.plls_con[ABPLL_ID], ABPLL_ID); 404 save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID); 405 406 restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]); 407 } 408 409 void restore_abpll(void) 410 { 411 restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]); 412 } 413 414 void restore_dpll(void) 415 { 416 restore_pll(DPLL_ID, slp_data.plls_con[DPLL_ID]); 417 } 418 419 void clk_gate_con_save(void) 420 { 421 uint32_t i = 0; 422 423 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 424 slp_data.pmucru_gate_con[i] = 425 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); 426 427 for (i = 0; i < CRU_GATE_COUNT; i++) 428 slp_data.cru_gate_con[i] = 429 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); 430 } 431 432 void clk_gate_con_disable(void) 433 { 434 uint32_t i; 435 436 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 437 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); 438 439 for (i = 0; i < CRU_GATE_COUNT; i++) 440 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); 441 } 442 443 void clk_gate_con_restore(void) 444 { 445 uint32_t i; 446 447 for (i = 0; i < PMUCRU_GATE_COUNT; i++) 448 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), 449 REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); 450 451 for (i = 0; i < CRU_GATE_COUNT; i++) 452 mmio_write_32(CRU_BASE + CRU_GATE_CON(i), 453 REG_SOC_WMSK | slp_data.cru_gate_con[i]); 454 } 455 456 static void set_plls_nobypass(uint32_t pll_id) 457 { 458 if (pll_id == PPLL_ID) 459 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), 460 PLL_NO_BYPASS_MODE); 461 else 462 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), 463 PLL_NO_BYPASS_MODE); 464 } 465 466 static void _pll_resume(uint32_t pll_id) 467 { 468 set_plls_nobypass(pll_id); 469 set_pll_normal_mode(pll_id); 470 } 471 472 /** 473 * enable_dvfs_plls - To resume the specific PLLs 474 * 475 * Please see the comment at the disable_dvfs_plls() 476 * we don't suspend the ABPLL, so don't need resume 477 * it too. 478 */ 479 void enable_dvfs_plls(void) 480 { 481 _pll_resume(ALPLL_ID); 482 _pll_resume(GPLL_ID); 483 _pll_resume(VPLL_ID); 484 _pll_resume(NPLL_ID); 485 _pll_resume(CPLL_ID); 486 } 487 488 /** 489 * enable_nodvfs_plls - To resume the PPLL 490 */ 491 void enable_nodvfs_plls(void) 492 { 493 _pll_resume(PPLL_ID); 494 } 495 496 void soc_global_soft_reset_init(void) 497 { 498 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 499 CRU_PMU_SGRF_RST_RLS); 500 501 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, 502 CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); 503 } 504 505 void __dead2 soc_global_soft_reset(void) 506 { 507 set_pll_slow_mode(VPLL_ID); 508 set_pll_slow_mode(NPLL_ID); 509 set_pll_slow_mode(GPLL_ID); 510 set_pll_slow_mode(CPLL_ID); 511 set_pll_slow_mode(PPLL_ID); 512 set_pll_slow_mode(ABPLL_ID); 513 set_pll_slow_mode(ALPLL_ID); 514 515 dsb(); 516 517 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 518 519 /* 520 * Maybe the HW needs some times to reset the system, 521 * so we do not hope the core to excute valid codes. 522 */ 523 while (1) 524 ; 525 } 526 527 void plat_rockchip_soc_init(void) 528 { 529 secure_timer_init(); 530 dma_secure_cfg(0); 531 sgrf_init(); 532 secure_sgrf_ddr_rgn_init(); 533 soc_global_soft_reset_init(); 534 plat_rockchip_gpio_init(); 535 m0_init(); 536 dram_init(); 537 dram_dfs_init(); 538 } 539