1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_PRIVATE_H__ 32 #define __PLAT_PRIVATE_H__ 33 34 #ifndef __ASSEMBLY__ 35 #include <mmio.h> 36 #include <stdint.h> 37 #include <xlat_tables.h> 38 #include <psci.h> 39 40 #define __sramdata __attribute__((section(".sram.data"))) 41 #define __sramconst __attribute__((section(".sram.rodata"))) 42 #define __sramfunc __attribute__((section(".sram.text"))) \ 43 __attribute__((noinline)) 44 45 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 46 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 47 48 /****************************************************************************** 49 * For rockchip socs pm ops 50 ******************************************************************************/ 51 struct rockchip_pm_ops_cb { 52 int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint); 53 int (*cores_pwr_dm_off)(void); 54 int (*cores_pwr_dm_on_finish)(void); 55 int (*cores_pwr_dm_suspend)(void); 56 int (*cores_pwr_dm_resume)(void); 57 /* hlvl is used for clusters or system level */ 58 int (*hlvl_pwr_dm_suspend)(uint32_t lvl, plat_local_state_t lvl_state); 59 int (*hlvl_pwr_dm_resume)(uint32_t lvl, plat_local_state_t lvl_state); 60 int (*hlvl_pwr_dm_off)(uint32_t lvl, plat_local_state_t lvl_state); 61 int (*hlvl_pwr_dm_on_finish)(uint32_t lvl, 62 plat_local_state_t lvl_state); 63 int (*sys_pwr_dm_suspend)(void); 64 int (*sys_pwr_dm_resume)(void); 65 void (*sys_gbl_soft_reset)(void) __dead2; 66 void (*system_off)(void) __dead2; 67 void (*sys_pwr_down_wfi)(const psci_power_state_t *state_info) __dead2; 68 }; 69 70 /****************************************************************************** 71 * The register have write-mask bits, it is mean, if you want to set the bits, 72 * you needs set the write-mask bits at the same time, 73 * The write-mask bits is in high 16-bits. 74 * The fllowing macro definition helps access write-mask bits reg efficient! 75 ******************************************************************************/ 76 #define REG_MSK_SHIFT 16 77 78 #ifndef WMSK_BIT 79 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 80 #endif 81 82 /* set one bit with write mask */ 83 #ifndef BIT_WITH_WMSK 84 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 85 #endif 86 87 #ifndef BITS_SHIFT 88 #define BITS_SHIFT(bits, shift) (bits << (shift)) 89 #endif 90 91 #ifndef BITS_WITH_WMASK 92 #define BITS_WITH_WMASK(bits, msk, shift)\ 93 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 94 #endif 95 96 /****************************************************************************** 97 * Function and variable prototypes 98 *****************************************************************************/ 99 void plat_configure_mmu_el3(unsigned long total_base, 100 unsigned long total_size, 101 unsigned long, 102 unsigned long, 103 unsigned long, 104 unsigned long); 105 106 void plat_cci_init(void); 107 void plat_cci_enable(void); 108 void plat_cci_disable(void); 109 110 void plat_delay_timer_init(void); 111 112 void params_early_setup(void *plat_params_from_bl2); 113 114 void plat_rockchip_gic_driver_init(void); 115 void plat_rockchip_gic_init(void); 116 void plat_rockchip_gic_cpuif_enable(void); 117 void plat_rockchip_gic_cpuif_disable(void); 118 void plat_rockchip_gic_pcpu_init(void); 119 120 void plat_rockchip_pmusram_prepare(void); 121 void plat_rockchip_pmu_init(void); 122 void plat_rockchip_soc_init(void); 123 void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops); 124 uintptr_t plat_get_sec_entrypoint(void); 125 126 void platform_cpu_warmboot(void); 127 128 struct gpio_info *plat_get_rockchip_gpio_reset(void); 129 struct gpio_info *plat_get_rockchip_gpio_poweroff(void); 130 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 131 struct apio_info *plat_get_rockchip_suspend_apio(void); 132 void plat_rockchip_gpio_init(void); 133 134 extern const unsigned char rockchip_power_domain_tree_desc[]; 135 136 extern void *pmu_cpuson_entrypoint_start; 137 extern void *pmu_cpuson_entrypoint_end; 138 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 139 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 140 141 extern const mmap_region_t plat_rk_mmap[]; 142 143 void rockchip_plat_sram_mmu_el3(void); 144 void plat_rockchip_mem_prepare(void); 145 146 #endif /* __ASSEMBLY__ */ 147 148 /****************************************************************************** 149 * cpu up status 150 * The bits of macro value is not more than 12 bits for cmp instruction! 151 ******************************************************************************/ 152 #define PMU_CPU_HOTPLUG 0xf00 153 #define PMU_CPU_AUTO_PWRDN 0xf0 154 #define PMU_CLST_RET 0xa5 155 156 #endif /* __PLAT_PRIVATE_H__ */ 157