1/* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34#include <denver.h> 35#include <cpu_macros.S> 36#include <plat_macros.S> 37 38 /* --------------------------------------------- 39 * Disable debug interfaces 40 * --------------------------------------------- 41 */ 42func denver_disable_ext_debug 43 mov x0, #1 44 msr osdlr_el1, x0 45 isb 46 dsb sy 47 ret 48endfunc denver_disable_ext_debug 49 50 /* ---------------------------------------------------- 51 * Enable dynamic code optimizer (DCO) 52 * ---------------------------------------------------- 53 */ 54func denver_enable_dco 55 mrs x0, mpidr_el1 56 and x0, x0, #0xF 57 mov x1, #1 58 lsl x1, x1, x0 59 msr s3_0_c15_c0_2, x1 60 isb 61 ret 62endfunc denver_enable_dco 63 64 /* ---------------------------------------------------- 65 * Disable dynamic code optimizer (DCO) 66 * ---------------------------------------------------- 67 */ 68func denver_disable_dco 69 70 /* turn off background work */ 71 mrs x0, mpidr_el1 72 and x0, x0, #0xF 73 mov x1, #1 74 lsl x1, x1, x0 75 lsl x2, x1, #16 76 msr s3_0_c15_c0_2, x2 77 isb 78 79 /* wait till the background work turns off */ 801: mrs x2, s3_0_c15_c0_2 81 lsr x2, x2, #32 82 and w2, w2, 0xFFFF 83 and x2, x2, x1 84 cbnz x2, 1b 85 86 ret 87endfunc denver_disable_dco 88 89 /* ------------------------------------------------- 90 * The CPU Ops reset function for Denver. 91 * ------------------------------------------------- 92 */ 93func denver_reset_func 94 95 mov x19, x30 96 97 /* ---------------------------------------------------- 98 * Enable dynamic code optimizer (DCO) 99 * ---------------------------------------------------- 100 */ 101 bl denver_enable_dco 102 103 ret x19 104endfunc denver_reset_func 105 106 /* ---------------------------------------------------- 107 * The CPU Ops core power down function for Denver. 108 * ---------------------------------------------------- 109 */ 110func denver_core_pwr_dwn 111 112 mov x19, x30 113 114 /* ---------------------------------------------------- 115 * We enter the 'core power gated with ARM state not 116 * retained' power state during CPU power down. We let 117 * DCO know that we expect to enter this power state 118 * by writing to the ACTLR_EL1 register. 119 * ---------------------------------------------------- 120 */ 121 mov x0, #DENVER_CPU_STATE_POWER_DOWN 122 msr actlr_el1, x0 123 124 /* --------------------------------------------- 125 * Force DCO to be quiescent 126 * --------------------------------------------- 127 */ 128 bl denver_disable_dco 129 130 /* --------------------------------------------- 131 * Force the debug interfaces to be quiescent 132 * --------------------------------------------- 133 */ 134 bl denver_disable_ext_debug 135 136 ret x19 137endfunc denver_core_pwr_dwn 138 139 /* ------------------------------------------------------- 140 * The CPU Ops cluster power down function for Denver. 141 * ------------------------------------------------------- 142 */ 143func denver_cluster_pwr_dwn 144 ret 145endfunc denver_cluster_pwr_dwn 146 147 /* --------------------------------------------- 148 * This function provides Denver specific 149 * register information for crash reporting. 150 * It needs to return with x6 pointing to 151 * a list of register names in ascii and 152 * x8 - x15 having values of registers to be 153 * reported. 154 * --------------------------------------------- 155 */ 156.section .rodata.denver_regs, "aS" 157denver_regs: /* The ascii list of register names to be reported */ 158 .asciz "actlr_el1", "" 159 160func denver_cpu_reg_dump 161 adr x6, denver_regs 162 mrs x8, ACTLR_EL1 163 ret 164endfunc denver_cpu_reg_dump 165 166declare_cpu_ops denver, DENVER_1_0_MIDR, \ 167 denver_reset_func, \ 168 denver_core_pwr_dwn, \ 169 denver_cluster_pwr_dwn 170