1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_H 8 #define PSCI_H 9 10 #include <bakery_lock.h> 11 #include <bl_common.h> 12 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 13 #if ENABLE_PLAT_COMPAT 14 #include <psci_compat.h> 15 #endif 16 #include <psci_lib.h> /* To maintain compatibility for SPDs */ 17 #include <utils_def.h> 18 19 /******************************************************************************* 20 * Number of power domains whose state this PSCI implementation can track 21 ******************************************************************************/ 22 #ifdef PLAT_NUM_PWR_DOMAINS 23 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 24 #else 25 #define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) 26 #endif 27 28 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 29 PLATFORM_CORE_COUNT) 30 31 /* This is the power level corresponding to a CPU */ 32 #define PSCI_CPU_PWR_LVL U(0) 33 34 /* 35 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 36 * uses the old power_state parameter format which has 2 bits to specify the 37 * power level, this constant is defined to be 3. 38 */ 39 #define PSCI_MAX_PWR_LVL U(3) 40 41 /******************************************************************************* 42 * Defines for runtime services function ids 43 ******************************************************************************/ 44 #define PSCI_VERSION U(0x84000000) 45 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 46 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 47 #define PSCI_CPU_OFF U(0x84000002) 48 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 49 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 50 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 51 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 52 #define PSCI_MIG_AARCH32 U(0x84000005) 53 #define PSCI_MIG_AARCH64 U(0xc4000005) 54 #define PSCI_MIG_INFO_TYPE U(0x84000006) 55 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 56 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 57 #define PSCI_SYSTEM_OFF U(0x84000008) 58 #define PSCI_SYSTEM_RESET U(0x84000009) 59 #define PSCI_FEATURES U(0x8400000A) 60 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 61 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 62 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 63 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 64 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 65 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 66 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 67 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 68 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 69 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 70 #define PSCI_MEM_PROTECT U(0x84000013) 71 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 72 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 73 74 /* 75 * Number of PSCI calls (above) implemented 76 */ 77 #if ENABLE_PSCI_STAT 78 #define PSCI_NUM_CALLS U(22) 79 #else 80 #define PSCI_NUM_CALLS U(18) 81 #endif 82 83 /* The macros below are used to identify PSCI calls from the SMC function ID */ 84 #define PSCI_FID_MASK U(0xffe0) 85 #define PSCI_FID_VALUE U(0) 86 #define is_psci_fid(_fid) \ 87 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 88 89 /******************************************************************************* 90 * PSCI Migrate and friends 91 ******************************************************************************/ 92 #define PSCI_TOS_UP_MIG_CAP 0 93 #define PSCI_TOS_NOT_UP_MIG_CAP 1 94 #define PSCI_TOS_NOT_PRESENT_MP 2 95 96 /******************************************************************************* 97 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 98 ******************************************************************************/ 99 #define PSTATE_ID_SHIFT U(0) 100 101 #if PSCI_EXTENDED_STATE_ID 102 #define PSTATE_VALID_MASK U(0xB0000000) 103 #define PSTATE_TYPE_SHIFT U(30) 104 #define PSTATE_ID_MASK U(0xfffffff) 105 #else 106 #define PSTATE_VALID_MASK U(0xFCFE0000) 107 #define PSTATE_TYPE_SHIFT U(16) 108 #define PSTATE_PWR_LVL_SHIFT U(24) 109 #define PSTATE_ID_MASK U(0xffff) 110 #define PSTATE_PWR_LVL_MASK U(0x3) 111 112 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 113 PSTATE_PWR_LVL_MASK) 114 #define psci_make_powerstate(state_id, type, pwrlvl) \ 115 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 116 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 117 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 118 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 119 120 #define PSTATE_TYPE_STANDBY U(0x0) 121 #define PSTATE_TYPE_POWERDOWN U(0x1) 122 #define PSTATE_TYPE_MASK U(0x1) 123 124 /******************************************************************************* 125 * PSCI CPU_FEATURES feature flag specific defines 126 ******************************************************************************/ 127 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 128 #define FF_PSTATE_SHIFT U(1) 129 #define FF_PSTATE_ORIG U(0) 130 #define FF_PSTATE_EXTENDED U(1) 131 #if PSCI_EXTENDED_STATE_ID 132 #define FF_PSTATE FF_PSTATE_EXTENDED 133 #else 134 #define FF_PSTATE FF_PSTATE_ORIG 135 #endif 136 137 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 138 #define FF_MODE_SUPPORT_SHIFT U(0) 139 #define FF_SUPPORTS_OS_INIT_MODE U(1) 140 141 /******************************************************************************* 142 * PSCI version 143 ******************************************************************************/ 144 #define PSCI_MAJOR_VER (U(1) << 16) 145 #define PSCI_MINOR_VER U(0x1) 146 147 /******************************************************************************* 148 * PSCI error codes 149 ******************************************************************************/ 150 #define PSCI_E_SUCCESS 0 151 #define PSCI_E_NOT_SUPPORTED -1 152 #define PSCI_E_INVALID_PARAMS -2 153 #define PSCI_E_DENIED -3 154 #define PSCI_E_ALREADY_ON -4 155 #define PSCI_E_ON_PENDING -5 156 #define PSCI_E_INTERN_FAIL -6 157 #define PSCI_E_NOT_PRESENT -7 158 #define PSCI_E_DISABLED -8 159 #define PSCI_E_INVALID_ADDRESS -9 160 161 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 162 163 /* 164 * SYSTEM_RESET2 macros 165 */ 166 #define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) 167 #define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 168 #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 169 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) 170 171 #ifndef __ASSEMBLY__ 172 173 #include <stdint.h> 174 #include <types.h> 175 176 /* Function to help build the psci capabilities bitfield */ 177 178 static inline unsigned int define_psci_cap(unsigned int x) 179 { 180 return U(1) << (x & U(0x1f)); 181 } 182 183 184 /* Power state helper functions */ 185 186 static inline unsigned int psci_get_pstate_id(unsigned int power_state) 187 { 188 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK; 189 } 190 191 static inline unsigned int psci_get_pstate_type(unsigned int power_state) 192 { 193 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK; 194 } 195 196 static inline unsigned int psci_check_power_state(unsigned int power_state) 197 { 198 return ((power_state) & PSTATE_VALID_MASK); 199 } 200 201 /* 202 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 203 * CPU. The definitions of these states can be found in Section 5.7.1 in the 204 * PSCI specification (ARM DEN 0022C). 205 */ 206 typedef enum { 207 AFF_STATE_ON = U(0), 208 AFF_STATE_OFF = U(1), 209 AFF_STATE_ON_PENDING = U(2) 210 } aff_info_state_t; 211 212 /* 213 * These are the power states reported by PSCI_NODE_HW_STATE API for the 214 * specified CPU. The definitions of these states can be found in Section 5.15.3 215 * of PSCI specification (ARM DEN 0022C). 216 */ 217 #define HW_ON 0 218 #define HW_OFF 1 219 #define HW_STANDBY 2 220 221 /* 222 * Macro to represent invalid affinity level within PSCI. 223 */ 224 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 225 226 /* 227 * Type for representing the local power state at a particular level. 228 */ 229 typedef uint8_t plat_local_state_t; 230 231 /* The local state macro used to represent RUN state. */ 232 #define PSCI_LOCAL_STATE_RUN U(0) 233 234 /* 235 * Function to test whether the plat_local_state is RUN state 236 */ 237 static inline int is_local_state_run(unsigned int plat_local_state) 238 { 239 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0; 240 } 241 242 /* 243 * Function to test whether the plat_local_state is RETENTION state 244 */ 245 static inline int is_local_state_retn(unsigned int plat_local_state) 246 { 247 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) && 248 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0; 249 } 250 251 /* 252 * Function to test whether the plat_local_state is OFF state 253 */ 254 static inline int is_local_state_off(unsigned int plat_local_state) 255 { 256 return ((plat_local_state > PLAT_MAX_RET_STATE) && 257 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0; 258 } 259 260 /***************************************************************************** 261 * This data structure defines the representation of the power state parameter 262 * for its exchange between the generic PSCI code and the platform port. For 263 * example, it is used by the platform port to specify the requested power 264 * states during a power management operation. It is used by the generic code to 265 * inform the platform about the target power states that each level should 266 * enter. 267 ****************************************************************************/ 268 typedef struct psci_power_state { 269 /* 270 * The pwr_domain_state[] stores the local power state at each level 271 * for the CPU. 272 */ 273 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 274 } psci_power_state_t; 275 276 /******************************************************************************* 277 * Structure used to store per-cpu information relevant to the PSCI service. 278 * It is populated in the per-cpu data array. In return we get a guarantee that 279 * this information will not reside on a cache line shared with another cpu. 280 ******************************************************************************/ 281 typedef struct psci_cpu_data { 282 /* State as seen by PSCI Affinity Info API */ 283 aff_info_state_t aff_info_state; 284 285 /* 286 * Highest power level which takes part in a power management 287 * operation. 288 */ 289 unsigned int target_pwrlvl; 290 291 /* The local power state of this CPU */ 292 plat_local_state_t local_state; 293 } psci_cpu_data_t; 294 295 /******************************************************************************* 296 * Structure populated by platform specific code to export routines which 297 * perform common low level power management functions 298 ******************************************************************************/ 299 typedef struct plat_psci_ops { 300 void (*cpu_standby)(plat_local_state_t cpu_state); 301 int (*pwr_domain_on)(u_register_t mpidr); 302 void (*pwr_domain_off)(const psci_power_state_t *target_state); 303 void (*pwr_domain_suspend_pwrdown_early)( 304 const psci_power_state_t *target_state); 305 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 306 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 307 void (*pwr_domain_suspend_finish)( 308 const psci_power_state_t *target_state); 309 void (*pwr_domain_pwr_down_wfi)( 310 const psci_power_state_t *target_state) __dead2; 311 void (*system_off)(void) __dead2; 312 void (*system_reset)(void) __dead2; 313 int (*validate_power_state)(unsigned int power_state, 314 psci_power_state_t *req_state); 315 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 316 void (*get_sys_suspend_power_state)( 317 psci_power_state_t *req_state); 318 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 319 int pwrlvl); 320 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 321 unsigned int power_state, 322 psci_power_state_t *output_state); 323 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 324 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 325 int (*read_mem_protect)(int *val); 326 int (*write_mem_protect)(int val); 327 int (*system_reset2)(int is_vendor, 328 int reset_type, u_register_t cookie); 329 } plat_psci_ops_t; 330 331 /******************************************************************************* 332 * Function & Data prototypes 333 ******************************************************************************/ 334 unsigned int psci_version(void); 335 int psci_cpu_on(u_register_t target_cpu, 336 uintptr_t entrypoint, 337 u_register_t context_id); 338 int psci_cpu_suspend(unsigned int power_state, 339 uintptr_t entrypoint, 340 u_register_t context_id); 341 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 342 int psci_cpu_off(void); 343 int psci_affinity_info(u_register_t target_affinity, 344 unsigned int lowest_affinity_level); 345 int psci_migrate(u_register_t target_cpu); 346 int psci_migrate_info_type(void); 347 long psci_migrate_info_up_cpu(void); 348 int psci_node_hw_state(u_register_t target_cpu, 349 unsigned int power_level); 350 int psci_features(unsigned int psci_fid); 351 void __dead2 psci_power_down_wfi(void); 352 void psci_arch_setup(void); 353 354 /* 355 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 356 * AArch64. 357 */ 358 void psci_entrypoint(void) __deprecated; 359 360 #endif /*__ASSEMBLY__*/ 361 362 #endif /* PSCI_H */ 363