1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <m0_param.h> 32 #include "rk3399_mcu.h" 33 34 /* PMU */ 35 #define PMU_PWRDN_ST 0x18 36 #define PMU_BUS_IDLE_REQ 0x60 37 #define PMU_BUS_IDLE_ST 0x64 38 #define PMU_NOC_AUTO_ENA 0xd8 39 40 /* PMU_BUS_IDLE_REQ */ 41 #define IDLE_REQ_MSCH1 (1 << 19) 42 #define IDLE_REQ_MSCH0 (1 << 18) 43 44 /* #define PMU_BUS_IDLE_ST */ 45 #define IDLE_MSCH1 (1 << 19) 46 #define IDLE_MSCH0 (1 << 18) 47 48 #define PD_VOP_PWR_STAT (1 << 20) 49 50 /* CRU */ 51 #define CRU_DPLL_CON0 0x40 52 #define CRU_DPLL_CON1 0x44 53 #define CRU_DPLL_CON2 0x48 54 #define CRU_DPLL_CON3 0x4c 55 #define CRU_DPLL_CON4 0x50 56 #define CRU_DPLL_CON5 0x54 57 58 #define CRU_DPLL_CON2 0x48 59 #define CRU_DPLL_CON3 0x4c 60 #define CRU_CLKGATE10_CON 0x328 61 #define CRU_CLKGATE28_CON 0x370 62 63 /* CRU_CLKGATE10_CON */ 64 #define ACLK_VOP0_PRE_SRC_EN (1 << 8) 65 #define HCLK_VOP0_PRE_EN (1 << 9) 66 #define ACLK_VOP1_PRE_SRC_EN (1 << 10) 67 #define HCLK_VOP1_PRE_EN (1 << 11) 68 #define DCLK_VOP0_SRC_EN (1 << 12) 69 #define DCLK_VOP1_SRC_EN (1 << 13) 70 71 /* CRU_CLKGATE28_CON */ 72 #define HCLK_VOP0_EN (1 << 2) 73 #define ACLK_VOP0_EN (1 << 3) 74 #define HCLK_VOP1_EN (1 << 6) 75 #define ACLK_VOP1_EN (1 << 7) 76 77 /* CRU_PLL_CON3 */ 78 #define PLL_SLOW_MODE 0 79 #define PLL_NORMAL_MODE 1 80 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) 81 #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) 82 83 /* PMU CRU */ 84 #define PMU_CRU_GATEDIS_CON0 0x130 85 86 /* VOP */ 87 #define VOP_SYS_CTRL 0x8 88 #define VOP_SYS_CTRL1 0xc 89 #define VOP_INTR_CLEAR0 0x284 90 #define VOP_INTR_RAW_STATUS0 0x28c 91 92 /* VOP_SYS_CTRL */ 93 #define VOP_STANDBY_EN (1 << 22) 94 95 /* VOP_INTR_CLEAR0 */ 96 #define INT_CLR_DMA_FINISH (1 << 15) 97 #define INT_CLR_LINE_FLAG1 (1 << 4) 98 #define INT_CLR_LINE_FLAG0 (1 << 3) 99 100 /* VOP_INTR_RAW_STATUS0 */ 101 #define INT_RAW_STATUS_DMA_FINISH (1 << 15) 102 #define INT_RAW_STATUS_LINE_FLAG1 (1 << 4) 103 #define INT_RAW_STATUS_LINE_FLAG0 (1 << 3) 104 105 /* CIC */ 106 #define CIC_CTRL0 0 107 #define CIC_CTRL1 0x4 108 #define CIC_STATUS0 0x10 109 110 struct ddr_freq_param { 111 uint32_t vop_big_en; 112 uint32_t vop_lit_en; 113 uint32_t dclk0_div; 114 uint32_t dclk1_div; 115 }; 116 117 static struct ddr_freq_param rk3399_ddr_arg; 118 119 static void get_vop_status(void) 120 { 121 rk3399_ddr_arg.vop_big_en = 0; 122 rk3399_ddr_arg.vop_lit_en = 0; 123 124 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & PD_VOP_PWR_STAT) == 0) { 125 /* get vop0 status */ 126 if ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE10_CON) & 127 (DCLK_VOP0_SRC_EN | ACLK_VOP0_PRE_SRC_EN | 128 HCLK_VOP0_PRE_EN)) == 0) 129 if ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE28_CON) & 130 (HCLK_VOP0_EN | ACLK_VOP0_EN)) == 0) 131 if ((mmio_read_32(VOP_BIG_BASE_ADDR + 132 VOP_SYS_CTRL) & 133 VOP_STANDBY_EN) == 0) 134 rk3399_ddr_arg.vop_big_en = 1; 135 136 /* get vop1 satus */ 137 if ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE10_CON) & 138 (DCLK_VOP1_SRC_EN | ACLK_VOP1_PRE_SRC_EN | 139 HCLK_VOP1_PRE_EN)) == 0) 140 if ((mmio_read_32(CRU_BASE_ADDR + CRU_CLKGATE28_CON) & 141 (HCLK_VOP1_EN | ACLK_VOP1_EN)) == 0) 142 if ((mmio_read_32(VOP_LITE_BASE_ADDR + 143 VOP_SYS_CTRL) & 144 VOP_STANDBY_EN) == 0) 145 rk3399_ddr_arg.vop_lit_en = 1; 146 } 147 } 148 149 static void wait_vop_dma_finish(void) 150 { 151 uint32_t vop_adr; 152 153 get_vop_status(); 154 155 if (rk3399_ddr_arg.vop_big_en) 156 vop_adr = VOP_BIG_BASE_ADDR; 157 else if (rk3399_ddr_arg.vop_lit_en) 158 vop_adr = VOP_LITE_BASE_ADDR; 159 else 160 return; 161 162 /* clean dma finish irq and wait for it */ 163 mmio_write_32(vop_adr + VOP_INTR_CLEAR0, 164 INT_CLR_DMA_FINISH | (INT_CLR_DMA_FINISH << 16)); 165 166 while ((mmio_read_32(vop_adr + VOP_INTR_RAW_STATUS0) & 167 INT_RAW_STATUS_DMA_FINISH) == 0) 168 ; 169 } 170 171 static void idle_port(void) 172 { 173 mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 174 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 175 IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); 176 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 177 (IDLE_MSCH1 | IDLE_MSCH0)) != (IDLE_MSCH1 | IDLE_MSCH0)) 178 continue; 179 } 180 181 static void deidle_port(void) 182 { 183 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 184 IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1); 185 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 186 (IDLE_MSCH1 | IDLE_MSCH0)) 187 continue; 188 } 189 190 static void ddr_set_pll(void) 191 { 192 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 193 194 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 195 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON0, 196 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 197 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON1, 198 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 199 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 200 201 while ((mmio_read_32(CRU_BASE_ADDR + CRU_DPLL_CON2) & (1u << 31)) == 0) 202 continue; 203 204 mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 205 } 206 207 void handle_dram(void) 208 { 209 wait_vop_dma_finish(); 210 idle_port(); 211 212 mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 213 (((0x3 << 4) | (1 << 2) | 1) << 16) | 214 (1 << 2) | 1 | 215 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 216 while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 2)) == 0) 217 continue; 218 219 ddr_set_pll(); 220 mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 0x20002); 221 while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 0)) == 0) 222 continue; 223 224 deidle_port(); 225 } 226