1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <bakery_lock.h> 13 #include <bl_common.h> 14 #include <cpu_data.h> 15 #include <psci.h> 16 #include <spinlock.h> 17 18 /* 19 * The PSCI capability which are provided by the generic code but does not 20 * depend on the platform or spd capabilities. 21 */ 22 #define PSCI_GENERIC_CAP \ 23 (define_psci_cap(PSCI_VERSION) | \ 24 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 25 define_psci_cap(PSCI_FEATURES)) 26 27 /* 28 * The PSCI capabilities mask for 64 bit functions. 29 */ 30 #define PSCI_CAP_64BIT_MASK \ 31 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 32 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 33 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 34 define_psci_cap(PSCI_MIG_AARCH64) | \ 35 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 36 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 37 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 38 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 39 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 40 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 41 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 42 43 /* 44 * Helper functions to get/set the fields of PSCI per-cpu data. 45 */ 46 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 47 { 48 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 49 } 50 51 static inline aff_info_state_t psci_get_aff_info_state(void) 52 { 53 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 54 } 55 56 static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx) 57 { 58 return get_cpu_data_by_index((unsigned int)idx, 59 psci_svc_cpu_data.aff_info_state); 60 } 61 62 static inline void psci_set_aff_info_state_by_idx(int idx, 63 aff_info_state_t aff_state) 64 { 65 set_cpu_data_by_index((unsigned int)idx, 66 psci_svc_cpu_data.aff_info_state, aff_state); 67 } 68 69 static inline unsigned int psci_get_suspend_pwrlvl(void) 70 { 71 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 72 } 73 74 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 75 { 76 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 77 } 78 79 static inline void psci_set_cpu_local_state(plat_local_state_t state) 80 { 81 set_cpu_data(psci_svc_cpu_data.local_state, state); 82 } 83 84 static inline plat_local_state_t psci_get_cpu_local_state(void) 85 { 86 return get_cpu_data(psci_svc_cpu_data.local_state); 87 } 88 89 static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx) 90 { 91 return get_cpu_data_by_index((unsigned int)idx, 92 psci_svc_cpu_data.local_state); 93 } 94 95 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 96 static inline int is_cpu_standby_req(unsigned int is_power_down_state, 97 unsigned int retn_lvl) 98 { 99 return ((is_power_down_state == 0U) && (retn_lvl == 0U)) ? 1 : 0; 100 } 101 102 /******************************************************************************* 103 * The following two data structures implement the power domain tree. The tree 104 * is used to track the state of all the nodes i.e. power domain instances 105 * described by the platform. The tree consists of nodes that describe CPU power 106 * domains i.e. leaf nodes and all other power domains which are parents of a 107 * CPU power domain i.e. non-leaf nodes. 108 ******************************************************************************/ 109 typedef struct non_cpu_pwr_domain_node { 110 /* 111 * Index of the first CPU power domain node level 0 which has this node 112 * as its parent. 113 */ 114 int cpu_start_idx; 115 116 /* 117 * Number of CPU power domains which are siblings of the domain indexed 118 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 119 * -> cpu_start_idx + ncpus' have this node as their parent. 120 */ 121 unsigned int ncpus; 122 123 /* 124 * Index of the parent power domain node. 125 * TODO: Figure out whether to whether using pointer is more efficient. 126 */ 127 unsigned int parent_node; 128 129 plat_local_state_t local_state; 130 131 unsigned char level; 132 133 /* For indexing the psci_lock array*/ 134 unsigned char lock_index; 135 } non_cpu_pd_node_t; 136 137 typedef struct cpu_pwr_domain_node { 138 u_register_t mpidr; 139 140 /* 141 * Index of the parent power domain node. 142 * TODO: Figure out whether to whether using pointer is more efficient. 143 */ 144 unsigned int parent_node; 145 146 /* 147 * A CPU power domain does not require state coordination like its 148 * parent power domains. Hence this node does not include a bakery 149 * lock. A spinlock is required by the CPU_ON handler to prevent a race 150 * when multiple CPUs try to turn ON the same target CPU. 151 */ 152 spinlock_t cpu_lock; 153 } cpu_pd_node_t; 154 155 /******************************************************************************* 156 * The following are helpers and declarations of locks. 157 ******************************************************************************/ 158 #if HW_ASSISTED_COHERENCY 159 /* 160 * On systems where participant CPUs are cache-coherent, we can use spinlocks 161 * instead of bakery locks. 162 */ 163 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 164 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 165 166 /* One lock is required per non-CPU power domain node */ 167 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 168 169 /* 170 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 171 * as PSCI participants are cache-coherent, and there's no need for explicit 172 * cache maintenance operations or barriers to coordinate their state. 173 */ 174 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 175 size_t __unused size) 176 { 177 /* Empty */ 178 } 179 180 #define psci_flush_cpu_data(member) 181 #define psci_inv_cpu_data(member) 182 183 static inline void psci_dsbish(void) 184 { 185 /* Empty */ 186 } 187 188 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 189 { 190 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 191 } 192 193 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 194 { 195 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 196 } 197 198 #else /* if HW_ASSISTED_COHERENCY == 0 */ 199 /* 200 * Use bakery locks for state coordination as not all PSCI participants are 201 * cache coherent. 202 */ 203 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 204 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 205 206 /* One lock is required per non-CPU power domain node */ 207 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 208 209 /* 210 * If not all PSCI participants are cache-coherent, perform cache maintenance 211 * and issue barriers wherever required to coordinate state. 212 */ 213 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 214 { 215 flush_dcache_range(addr, size); 216 } 217 218 #define psci_flush_cpu_data(member) flush_cpu_data(member) 219 #define psci_inv_cpu_data(member) inv_cpu_data(member) 220 221 static inline void psci_dsbish(void) 222 { 223 dsbish(); 224 } 225 226 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 227 { 228 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 229 } 230 231 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 232 { 233 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 234 } 235 236 #endif /* HW_ASSISTED_COHERENCY */ 237 238 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 239 unsigned char idx) 240 { 241 non_cpu_pd_node[idx].lock_index = idx; 242 } 243 244 /******************************************************************************* 245 * Data prototypes 246 ******************************************************************************/ 247 extern const plat_psci_ops_t *psci_plat_pm_ops; 248 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 249 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 250 extern unsigned int psci_caps; 251 252 /******************************************************************************* 253 * SPD's power management hooks registered with PSCI 254 ******************************************************************************/ 255 extern const spd_pm_ops_t *psci_spd_pm; 256 257 /******************************************************************************* 258 * Function prototypes 259 ******************************************************************************/ 260 /* Private exported functions from psci_common.c */ 261 int psci_validate_power_state(unsigned int power_state, 262 psci_power_state_t *state_info); 263 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 264 int psci_validate_mpidr(u_register_t mpidr); 265 void psci_init_req_local_pwr_states(void); 266 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 267 psci_power_state_t *target_state); 268 int psci_validate_entry_point(entry_point_info_t *ep, 269 uintptr_t entrypoint, u_register_t context_id); 270 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 271 unsigned int end_lvl, 272 unsigned int node_index[]); 273 void psci_do_state_coordination(unsigned int end_pwrlvl, 274 psci_power_state_t *state_info); 275 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 276 unsigned int cpu_idx); 277 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 278 unsigned int cpu_idx); 279 int psci_validate_suspend_req(const psci_power_state_t *state_info, 280 unsigned int is_power_down_state); 281 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 282 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 283 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); 284 void psci_print_power_domain_map(void); 285 unsigned int psci_is_last_on_cpu(void); 286 int psci_spd_migrate_info(u_register_t *mpidr); 287 void psci_do_pwrdown_sequence(unsigned int power_level); 288 289 /* 290 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 291 * available. Otherwise, this needs post-call stack maintenance, which is 292 * handled in assembly. 293 */ 294 void prepare_cpu_pwr_dwn(unsigned int power_level); 295 296 /* Private exported functions from psci_on.c */ 297 int psci_cpu_on_start(u_register_t target_cpu, 298 entry_point_info_t *ep); 299 300 void psci_cpu_on_finish(unsigned int cpu_idx, 301 psci_power_state_t *state_info); 302 303 /* Private exported functions from psci_off.c */ 304 int psci_do_cpu_off(unsigned int end_pwrlvl); 305 306 /* Private exported functions from psci_suspend.c */ 307 void psci_cpu_suspend_start(entry_point_info_t *ep, 308 unsigned int end_pwrlvl, 309 psci_power_state_t *state_info, 310 unsigned int is_power_down_state); 311 312 void psci_cpu_suspend_finish(unsigned int cpu_idx, 313 psci_power_state_t *state_info); 314 315 /* Private exported functions from psci_helpers.S */ 316 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 317 void psci_do_pwrup_cache_maintenance(void); 318 319 /* Private exported functions from psci_system_off.c */ 320 void __dead2 psci_system_off(void); 321 void __dead2 psci_system_reset(void); 322 int psci_system_reset2(uint32_t reset_type, u_register_t cookie); 323 324 /* Private exported functions from psci_stat.c */ 325 void psci_stats_update_pwr_down(unsigned int end_pwrlvl, 326 const psci_power_state_t *state_info); 327 void psci_stats_update_pwr_up(unsigned int end_pwrlvl, 328 const psci_power_state_t *state_info); 329 u_register_t psci_stat_residency(u_register_t target_cpu, 330 unsigned int power_state); 331 u_register_t psci_stat_count(u_register_t target_cpu, 332 unsigned int power_state); 333 334 /* Private exported functions from psci_mem_protect.c */ 335 int psci_mem_protect(unsigned int enable); 336 int psci_mem_chk_range(uintptr_t base, u_register_t length); 337 338 #endif /* PSCI_PRIVATE_H */ 339