1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_H__ 32 #define __SOC_H__ 33 34 #include <utils.h> 35 36 #define GLB_SRST_FST_CFG_VAL 0xfdb9 37 #define GLB_SRST_SND_CFG_VAL 0xeca8 38 39 #define PMUCRU_PPLL_CON(n) ((n) * 4) 40 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 41 #define PLL_MODE_MSK 0x03 42 #define PLL_MODE_SHIFT 0x08 43 #define PLL_BYPASS_MSK 0x01 44 #define PLL_BYPASS_SHIFT 0x01 45 #define PLL_PWRDN_MSK 0x01 46 #define PLL_PWRDN_SHIFT 0x0 47 #define PLL_BYPASS BIT(1) 48 #define PLL_PWRDN BIT(0) 49 50 #define NO_PLL_BYPASS (0x00) 51 #define NO_PLL_PWRDN (0x00) 52 53 #define FBDIV(n) ((0xfff << 16) | n) 54 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 55 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 56 #define REFDIV(n) ((0x3F << 16) | n) 57 #define PLL_LOCK(n) ((n >> 31) & 0x1) 58 59 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 60 PLL_MODE_MSK, PLL_MODE_SHIFT) 61 62 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 63 PLL_MODE_MSK, PLL_MODE_SHIFT) 64 65 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 66 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 67 68 #define PLL_CON_COUNT 0x06 69 #define CRU_CLKSEL_COUNT 108 70 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) 71 72 #define PMUCRU_CLKSEL_CONUT 0x06 73 #define PMUCRU_CLKSEL_OFFSET 0x080 74 #define REG_SIZE 0x04 75 #define REG_SOC_WMSK 0xffff0000 76 #define CLK_GATE_MASK 0x01 77 78 #define SGRF_SOC_COUNT 0x17 79 #define PMUCRU_GATE_COUNT 0x03 80 #define CRU_GATE_COUNT 0x23 81 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 82 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 83 84 enum plls_id { 85 ALPLL_ID = 0, 86 ABPLL_ID, 87 DPLL_ID, 88 CPLL_ID, 89 GPLL_ID, 90 NPLL_ID, 91 VPLL_ID, 92 PPLL_ID, 93 END_PLL_ID, 94 }; 95 96 #define CLST_L_CPUS_MSK (0xf) 97 #define CLST_B_CPUS_MSK (0x3) 98 99 enum pll_work_mode { 100 SLOW_MODE = 0x00, 101 NORMAL_MODE = 0x01, 102 DEEP_SLOW_MODE = 0x02, 103 }; 104 105 enum glb_sft_reset { 106 PMU_RST_BY_FIRST_SFT, 107 PMU_RST_BY_SECOND_SFT = BIT(2), 108 PMU_RST_NOT_BY_SFT = BIT(3), 109 }; 110 111 struct pll_div { 112 uint32_t mhz; 113 uint32_t refdiv; 114 uint32_t fbdiv; 115 uint32_t postdiv1; 116 uint32_t postdiv2; 117 uint32_t frac; 118 uint32_t freq; 119 }; 120 121 struct deepsleep_data_s { 122 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 123 uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; 124 uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; 125 uint32_t cru_gate_con[CRU_GATE_COUNT]; 126 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 127 uint32_t sgrf_con[SGRF_SOC_COUNT]; 128 }; 129 130 /************************************************** 131 * pmugrf reg, offset 132 **************************************************/ 133 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 134 135 /************************************************** 136 * DCF reg, offset 137 **************************************************/ 138 #define DCF_DCF_CTRL 0x0 139 #define DCF_DCF_ADDR 0x8 140 #define DCF_DCF_ISR 0xc 141 #define DCF_DCF_TOSET 0x14 142 #define DCF_DCF_TOCMD 0x18 143 #define DCF_DCF_CMD_CFG 0x1c 144 145 /* DCF_DCF_ISR */ 146 #define DCF_TIMEOUT (1 << 2) 147 #define DCF_ERR (1 << 1) 148 #define DCF_DONE (1 << 0) 149 150 /* DCF_DCF_CTRL */ 151 #define DCF_VOP_HW_EN (1 << 2) 152 #define DCF_STOP (1 << 1) 153 #define DCF_START (1 << 0) 154 155 #define CYCL_24M_CNT_US(us) (24 * us) 156 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 157 #define CYCL_32K_CNT_MS(ms) (ms * 32) 158 159 /************************************************** 160 * secure timer 161 **************************************************/ 162 163 /* chanal0~5 */ 164 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 165 /* chanal6~11 */ 166 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 167 168 /* low 32 bits */ 169 #define TIMER_END_COUNT0 0x00 170 /* high 32 bits */ 171 #define TIMER_END_COUNT1 0x04 172 173 #define TIMER_CURRENT_VALUE0 0x08 174 #define TIMER_CURRENT_VALUE1 0x0C 175 176 /* low 32 bits */ 177 #define TIMER_INIT_COUNT0 0x10 178 /* high 32 bits */ 179 #define TIMER_INIT_COUNT1 0x14 180 181 #define TIMER_INTSTATUS 0x18 182 #define TIMER_CONTROL_REG 0x1c 183 184 #define TIMER_EN 0x1 185 186 #define TIMER_FMODE (0x0 << 1) 187 #define TIMER_RMODE (0x1 << 1) 188 189 /************************************************** 190 * secure WDT 191 **************************************************/ 192 #define WDT_CM0_EN 0x0 193 #define WDT_CM0_DIS 0x1 194 #define WDT_CA53_EN 0x0 195 #define WDT_CA53_DIS 0x1 196 197 #define PCLK_WDT_CA53_GATE_SHIFT 8 198 #define PCLK_WDT_CM0_GATE_SHIFT 10 199 200 #define WDT_CA53_1BIT_MASK 0x1 201 #define WDT_CM0_1BIT_MASK 0x1 202 203 /************************************************** 204 * cru reg, offset 205 **************************************************/ 206 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 207 208 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 209 /* reset release*/ 210 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 211 212 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 213 /* reset release*/ 214 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 215 216 #define CRU_GLB_RST_CON 0x0510 217 #define CRU_GLB_SRST_FST 0x0500 218 #define CRU_GLB_SRST_SND 0x0504 219 220 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 221 #define PCLK_GPIO2_GATE_SHIFT 3 222 #define PCLK_GPIO3_GATE_SHIFT 4 223 #define PCLK_GPIO4_GATE_SHIFT 5 224 225 /************************************************** 226 * pmu cru reg, offset 227 **************************************************/ 228 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 229 /* reset hold*/ 230 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 231 /* reset hold release*/ 232 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 233 234 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 235 #define CRU_PMU_WDTRST_EN 0x0 236 237 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 238 #define CRU_PMU_FIRST_SFTRST_EN 0x0 239 240 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 241 #define PCLK_GPIO0_GATE_SHIFT 3 242 #define PCLK_GPIO1_GATE_SHIFT 4 243 244 /************************************************** 245 * sgrf reg, offset 246 **************************************************/ 247 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 248 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 249 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 250 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 251 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 252 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 253 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 254 255 /* security config for master */ 256 #define SGRF_SOC_CON_WMSK 0xffff0000 257 /* All of master in ns */ 258 #define SGRF_SOC_ALLMST_NS 0xffff 259 260 /* security config for slave */ 261 #define SGRF_SLV_S_WMSK 0xffff0000 262 #define SGRF_SLV_S_ALL_NS 0x0 263 264 /* security config pmu slave ip */ 265 /* All of slaves is ns */ 266 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 267 /* slaves secure attr is configed */ 268 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 269 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 270 271 #define SGRF_PMUSRAM_S BIT(8) 272 273 #define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ 274 SGRF_PMUSRAM_S) 275 /* ddr region */ 276 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ 277 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ 278 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ 279 280 /* The MST access the ddr rgn n with secure attribution */ 281 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 282 /* bits[16:8]*/ 283 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 284 285 /* dmac to periph s or ns*/ 286 #define SGRF_DMAC_CFG_S 0xffff0000 287 288 #define DMAC1_RGN_NS 0xff000000 289 #define DMAC0_RGN_NS 0x00ff0000 290 291 #define DMAC0_BOOT_CFG_NS 0xfffffff8 292 #define DMAC0_BOOT_PERIPH_NS 0xffff0fff 293 #define DMAC0_BOOT_ADDR_NS 0xffff0000 294 295 #define DMAC1_BOOT_CFG_NS 0xffff0008 296 #define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff 297 #define DMAC1_BOOT_ADDR_NS 0xffff0000 298 #define DMAC1_BOOT_PERIPH_H_NS 0xffffffff 299 #define DMAC1_BOOT_IRQ_NS 0xffffffff 300 301 #define CPU_BOOT_ADDR_WMASK 0xffff0000 302 #define CPU_BOOT_ADDR_ALIGN 16 303 304 #define GRF_IOMUX_2BIT_MASK 0x3 305 #define GRF_IOMUX_GPIO 0x0 306 307 #define GRF_GPIO4C2_IOMUX_SHIFT 4 308 #define GRF_GPIO4C2_IOMUX_PWM 0x1 309 #define GRF_GPIO4C6_IOMUX_SHIFT 12 310 #define GRF_GPIO4C6_IOMUX_PWM 0x1 311 312 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 313 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 314 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 315 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 316 317 #define PWM_DISABLE (0 << 0) 318 #define PWM_ENABLE (1 << 0) 319 320 /* grf reg offset */ 321 #define GRF_DDRC0_CON0 0xe380 322 #define GRF_DDRC0_CON1 0xe384 323 #define GRF_DDRC1_CON0 0xe388 324 #define GRF_DDRC1_CON1 0xe38c 325 #define GRF_SOC_CON_BASE 0xe200 326 #define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) 327 328 #define PMUCRU_CLKSEL_CON0 0x0080 329 #define PMUCRU_CLKGATE_CON2 0x0108 330 #define PMUCRU_SOFTRST_CON0 0x0110 331 #define PMUCRU_GATEDIS_CON0 0x0130 332 333 #define SGRF_SOC_CON6 0x0e018 334 #define SGRF_PERILP_CON0 0x08100 335 #define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4) 336 #define SGRF_PMU_CON0 0x0c100 337 #define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) 338 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) 339 340 /* 341 * When system reset in running state, we want the cpus to be reboot 342 * from maskrom (system reboot), 343 * the pmusgrf reset-hold bits needs to be released. 344 * When system wake up from system deep suspend, some soc will be reset 345 * when waked up, 346 * we want the bootcpu to be reboot from pmusram, 347 * the pmusgrf reset-hold bits needs to be held. 348 */ 349 static inline void pmu_sgrf_rst_hld_release(void) 350 { 351 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 352 CRU_PMU_SGRF_RST_RLS); 353 } 354 355 static inline void pmu_sgrf_rst_hld(void) 356 { 357 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 358 CRU_PMU_SGRF_RST_HOLD); 359 } 360 361 /* funciton*/ 362 void __dead2 soc_global_soft_reset(void); 363 void secure_watchdog_disable(); 364 void secure_watchdog_restore(); 365 void disable_dvfs_plls(void); 366 void disable_nodvfs_plls(void); 367 void enable_dvfs_plls(void); 368 void enable_nodvfs_plls(void); 369 void prepare_abpll_for_ddrctrl(void); 370 void restore_abpll(void); 371 void restore_dpll(void); 372 void clk_gate_con_save(void); 373 void clk_gate_con_disable(void); 374 void clk_gate_con_restore(void); 375 void sgrf_init(void); 376 #endif /* __SOC_H__ */ 377