1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __DDR_RK3368_H__ 32 #define __DDR_RK3368_H__ 33 34 #define DDR_PCTL_SCFG 0x0 35 #define DDR_PCTL_SCTL 0x4 36 #define DDR_PCTL_STAT 0x8 37 #define DDR_PCTL_INTRSTAT 0xc 38 39 #define DDR_PCTL_MCMD 0x40 40 #define DDR_PCTL_POWCTL 0x44 41 #define DDR_PCTL_POWSTAT 0x48 42 #define DDR_PCTL_CMDTSTAT 0x4c 43 #define DDR_PCTL_CMDTSTATEN 0x50 44 #define DDR_PCTL_MRRCFG0 0x60 45 #define DDR_PCTL_MRRSTAT0 0x64 46 #define DDR_PCTL_MRRSTAT1 0x68 47 #define DDR_PCTL_MCFG1 0x7c 48 #define DDR_PCTL_MCFG 0x80 49 #define DDR_PCTL_PPCFG 0x84 50 #define DDR_PCTL_MSTAT 0x88 51 #define DDR_PCTL_LPDDR2ZQCFG 0x8c 52 #define DDR_PCTL_DTUPDES 0x94 53 #define DDR_PCTL_DTUNA 0x98 54 #define DDR_PCTL_DTUNE 0x9c 55 #define DDR_PCTL_DTUPRD0 0xa0 56 #define DDR_PCTL_DTUPRD1 0xa4 57 #define DDR_PCTL_DTUPRD2 0xa8 58 #define DDR_PCTL_DTUPRD3 0xac 59 #define DDR_PCTL_DTUAWDT 0xb0 60 #define DDR_PCTL_TOGCNT1U 0xc0 61 #define DDR_PCTL_TINIT 0xc4 62 #define DDR_PCTL_TRSTH 0xc8 63 #define DDR_PCTL_TOGCNT100N 0xcc 64 #define DDR_PCTL_TREFI 0xd0 65 #define DDR_PCTL_TMRD 0xd4 66 #define DDR_PCTL_TRFC 0xd8 67 #define DDR_PCTL_TRP 0xdc 68 #define DDR_PCTL_TRTW 0xe0 69 #define DDR_PCTL_TAL 0xe4 70 #define DDR_PCTL_TCL 0xe8 71 #define DDR_PCTL_TCWL 0xec 72 #define DDR_PCTL_TRAS 0xf0 73 #define DDR_PCTL_TRC 0xf4 74 #define DDR_PCTL_TRCD 0xf8 75 #define DDR_PCTL_TRRD 0xfc 76 #define DDR_PCTL_TRTP 0x100 77 #define DDR_PCTL_TWR 0x104 78 #define DDR_PCTL_TWTR 0x108 79 #define DDR_PCTL_TEXSR 0x10c 80 #define DDR_PCTL_TXP 0x110 81 #define DDR_PCTL_TXPDLL 0x114 82 #define DDR_PCTL_TZQCS 0x118 83 #define DDR_PCTL_TZQCSI 0x11c 84 #define DDR_PCTL_TDQS 0x120 85 #define DDR_PCTL_TCKSRE 0x124 86 #define DDR_PCTL_TCKSRX 0x128 87 #define DDR_PCTL_TCKE 0x12c 88 #define DDR_PCTL_TMOD 0x130 89 #define DDR_PCTL_TRSTL 0x134 90 #define DDR_PCTL_TZQCL 0x138 91 #define DDR_PCTL_TMRR 0x13c 92 #define DDR_PCTL_TCKESR 0x140 93 #define DDR_PCTL_TDPD 0x144 94 #define DDR_PCTL_TREFI_MEM_DDR3 0x148 95 #define DDR_PCTL_ECCCFG 0x180 96 #define DDR_PCTL_ECCTST 0x184 97 #define DDR_PCTL_ECCCLR 0x188 98 #define DDR_PCTL_ECCLOG 0x18c 99 #define DDR_PCTL_DTUWACTL 0x200 100 #define DDR_PCTL_DTURACTL 0x204 101 #define DDR_PCTL_DTUCFG 0x208 102 #define DDR_PCTL_DTUECTL 0x20c 103 #define DDR_PCTL_DTUWD0 0x210 104 #define DDR_PCTL_DTUWD1 0x214 105 #define DDR_PCTL_DTUWD2 0x218 106 #define DDR_PCTL_DTUWD3 0x21c 107 #define DDR_PCTL_DTUWDM 0x220 108 #define DDR_PCTL_DTURD0 0x224 109 #define DDR_PCTL_DTURD1 0x228 110 #define DDR_PCTL_DTURD2 0x22c 111 #define DDR_PCTL_DTURD3 0x230 112 #define DDR_PCTL_DTULFSRWD 0x234 113 #define DDR_PCTL_DTULFSRRD 0x238 114 #define DDR_PCTL_DTUEAF 0x23c 115 #define DDR_PCTL_DFITCTRLDELAY 0x240 116 #define DDR_PCTL_DFIODTCFG 0x244 117 #define DDR_PCTL_DFIODTCFG1 0x248 118 #define DDR_PCTL_DFIODTRANKMAP 0x24c 119 #define DDR_PCTL_DFITPHYWRDATA 0x250 120 #define DDR_PCTL_DFITPHYWRLAT 0x254 121 #define DDR_PCTL_DFITPHYWRDATALAT 0x258 122 #define DDR_PCTL_DFITRDDATAEN 0x260 123 #define DDR_PCTL_DFITPHYRDLAT 0x264 124 #define DDR_PCTL_DFITPHYUPDTYPE0 0x270 125 #define DDR_PCTL_DFITPHYUPDTYPE1 0x274 126 #define DDR_PCTL_DFITPHYUPDTYPE2 0x278 127 #define DDR_PCTL_DFITPHYUPDTYPE3 0x27c 128 #define DDR_PCTL_DFITCTRLUPDMIN 0x280 129 #define DDR_PCTL_DFITCTRLUPDMAX 0x284 130 #define DDR_PCTL_DFITCTRLUPDDLY 0x288 131 #define DDR_PCTL_DFIUPDCFG 0x290 132 #define DDR_PCTL_DFITREFMSKI 0x294 133 #define DDR_PCTL_DFITCTRLUPDI 0x298 134 #define DDR_PCTL_DFITRCFG0 0x2ac 135 #define DDR_PCTL_DFITRSTAT0 0x2b0 136 #define DDR_PCTL_DFITRWRLVLEN 0x2b4 137 #define DDR_PCTL_DFITRRDLVLEN 0x2b8 138 #define DDR_PCTL_DFITRRDLVLGATEEN 0x2bc 139 #define DDR_PCTL_DFISTSTAT0 0x2c0 140 #define DDR_PCTL_DFISTCFG0 0x2c4 141 #define DDR_PCTL_DFISTCFG1 0x2c8 142 #define DDR_PCTL_DFITDRAMCLKEN 0x2d0 143 #define DDR_PCTL_DFITDRAMCLKDIS 0x2d4 144 #define DDR_PCTL_DFISTCFG2 0x2d8 145 #define DDR_PCTL_DFISTPARCLR 0x2dc 146 #define DDR_PCTL_DFISTPARLOG 0x2e0 147 #define DDR_PCTL_DFILPCFG0 0x2f0 148 #define DDR_PCTL_DFITRWRLVLRESP0 0x300 149 #define DDR_PCTL_DFITRWRLVLRESP1 0x304 150 #define DDR_PCTL_DFITRWRLVLRESP2 0x308 151 #define DDR_PCTL_DFITRRDLVLRESP0 0x30c 152 #define DDR_PCTL_DFITRRDLVLRESP1 0x310 153 #define DDR_PCTL_DFITRRDLVLRESP2 0x314 154 #define DDR_PCTL_DFITRWRLVLDELAY0 0x318 155 #define DDR_PCTL_DFITRWRLVLDELAY1 0x31c 156 #define DDR_PCTL_DFITRWRLVLDELAY2 0x320 157 #define DDR_PCTL_DFITRRDLVLDELAY0 0x324 158 #define DDR_PCTL_DFITRRDLVLDELAY1 0x328 159 #define DDR_PCTL_DFITRRDLVLDELAY2 0x32c 160 #define DDR_PCTL_DFITRRDLVLGATEDELAY0 0x330 161 #define DDR_PCTL_DFITRRDLVLGATEDELAY1 0x334 162 #define DDR_PCTL_DFITRRDLVLGATEDELAY2 0x338 163 #define DDR_PCTL_DFITRCMD 0x33c 164 #define DDR_PCTL_IPVR 0x3f8 165 #define DDR_PCTL_IPTR 0x3fc 166 167 /* DDR PHY REG */ 168 #define DDR_PHY_REG0 0x0 169 #define DDR_PHY_REG1 0x4 170 #define DDR_PHY_REG2 0x8 171 #define DDR_PHY_REG3 0xc 172 #define DDR_PHY_REG4 0x10 173 #define DDR_PHY_REG5 0x14 174 #define DDR_PHY_REG6 0x18 175 #define DDR_PHY_REGB 0x2c 176 #define DDR_PHY_REGC 0x30 177 #define DDR_PHY_REG11 0x44 178 #define DDR_PHY_REG12 0x48 179 #define DDR_PHY_REG13 0x4c 180 #define DDR_PHY_REG14 0x50 181 #define DDR_PHY_REG16 0x58 182 #define DDR_PHY_REG20 0x80 183 #define DDR_PHY_REG21 0x84 184 #define DDR_PHY_REG26 0x98 185 #define DDR_PHY_REG27 0x9c 186 #define DDR_PHY_REG28 0xa0 187 #define DDR_PHY_REG2C 0xb0 188 #define DDR_PHY_REG30 0xc0 189 #define DDR_PHY_REG31 0xc4 190 #define DDR_PHY_REG36 0xd8 191 #define DDR_PHY_REG37 0xdc 192 #define DDR_PHY_REG38 0xe0 193 #define DDR_PHY_REG3C 0xf0 194 #define DDR_PHY_REG40 0x100 195 #define DDR_PHY_REG41 0x104 196 #define DDR_PHY_REG46 0x118 197 #define DDR_PHY_REG47 0x11c 198 #define DDR_PHY_REG48 0x120 199 #define DDR_PHY_REG4C 0x130 200 #define DDR_PHY_REG50 0x140 201 #define DDR_PHY_REG51 0x144 202 #define DDR_PHY_REG56 0x158 203 #define DDR_PHY_REG57 0x15c 204 #define DDR_PHY_REG58 0x160 205 #define DDR_PHY_REG5C 0x170 206 #define DDR_PHY_REGDLL 0x290 207 #define DDR_PHY_REGEC 0x3b0 208 #define DDR_PHY_REGED 0x3b4 209 #define DDR_PHY_REGEE 0x3b8 210 #define DDR_PHY_REGEF 0x3bc 211 #define DDR_PHY_REGF0 0x3c0 212 #define DDR_PHY_REGF1 0x3c4 213 #define DDR_PHY_REGF2 0x3c8 214 #define DDR_PHY_REGFA 0x3e8 215 #define DDR_PHY_REGFB 0x3ec 216 #define DDR_PHY_REGFC 0x3f0 217 #define DDR_PHY_REGFD 0x3f4 218 #define DDR_PHY_REGFE 0x3f8 219 #define DDR_PHY_REGFF 0x3fc 220 221 /* MSCH REG define */ 222 #define MSCH_COREID 0x0 223 #define MSCH_DDRCONF 0x8 224 #define MSCH_DDRTIMING 0xc 225 #define MSCH_DDRMODE 0x10 226 #define MSCH_READLATENCY 0x14 227 #define MSCH_ACTIVATE 0x38 228 #define MSCH_DEVTODEV 0x3c 229 230 #define SET_NR(n) ((0x3f << (8 + 16)) | ((n - 1) << 8)) 231 #define SET_NO(n) ((0xf << (0 + 16)) | ((n - 1) << 0)) 232 #define SET_NF(n) ((n - 1) & 0x1fff) 233 #define SET_NB(n) ((n - 1) & 0xfff) 234 #define PLLMODE(n) ((0x3 << (8 + 16)) | (n << 8)) 235 236 /* GRF REG define */ 237 #define GRF_SOC_STATUS0 0x480 238 #define GRF_DDRPHY_LOCK (0x1 << 15) 239 #define GRF_DDRC0_CON0 0x600 240 241 /* CRU softreset ddr pctl, phy */ 242 #define DDRMSCH0_SRSTN_REQ(n) (((0x1 << 10) << 16) | (n << 10)) 243 #define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3)) 244 #define DDRCTRL0_SRSTN_REQ(n) (((0x1 << 2) << 16) | (n << 2)) 245 #define DDRPHY0_PSRSTN_REQ(n) (((0x1 << 1) << 16) | (n << 1)) 246 #define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0)) 247 248 /* CRU_DPLL_CON2 */ 249 #define DPLL_STATUS_LOCK (1 << 31) 250 251 /* CRU_DPLL_CON3 */ 252 #define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1)) 253 #define DPLL_WORK_NORMAL_MODE ((0x3 << (8 + 16)) | (0 << 8)) 254 #define DPLL_WORK_SLOW_MODE ((0x3 << (8 + 16)) | (1 << 8)) 255 #define DPLL_RESET_CONTROL_NORMAL ((0x1 << (5 + 16)) | (0x0 << 5)) 256 #define DPLL_RESET_CONTROL_RESET ((0x1 << (5 + 16)) | (0x1 << 5)) 257 258 /* PMU_PWRDN_CON */ 259 #define PD_PERI_PWRDN_ENABLE (1 << 13) 260 261 #define DDR_PLL_SRC_MASK 0x13 262 263 /* DDR_PCTL_TREFI */ 264 #define DDR_UPD_REF_ENABLE (0X1 << 31) 265 266 uint32_t ddr_get_resume_code_size(void); 267 uint32_t ddr_get_resume_data_size(void); 268 uint32_t *ddr_get_resume_code_base(void); 269 void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr); 270 271 #endif 272