1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <interrupt_mgmt.h> 38 #include <platform.h> 39 #include <platform_def.h> 40 #include <smcc_helpers.h> 41 #include <string.h> 42 43 44 /******************************************************************************* 45 * Context management library initialisation routine. This library is used by 46 * runtime services to share pointers to 'cpu_context' structures for the secure 47 * and non-secure states. Management of the structures and their associated 48 * memory is not done by the context management library e.g. the PSCI service 49 * manages the cpu context used for entry from and exit to the non-secure state. 50 * The Secure payload dispatcher service manages the context(s) corresponding to 51 * the secure state. It also uses this library to get access to the non-secure 52 * state cpu context pointers. 53 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 54 * which will used for programming an entry into a lower EL. The same context 55 * will used to save state upon exception entry from that EL. 56 ******************************************************************************/ 57 void cm_init(void) 58 { 59 /* 60 * The context management library has only global data to intialize, but 61 * that will be done when the BSS is zeroed out 62 */ 63 } 64 65 /******************************************************************************* 66 * The following function initializes the cpu_context 'ctx' for 67 * first use, and sets the initial entrypoint state as specified by the 68 * entry_point_info structure. 69 * 70 * The security state to initialize is determined by the SECURE attribute 71 * of the entry_point_info. The function returns a pointer to the initialized 72 * context and sets this as the next context to return to. 73 * 74 * The EE and ST attributes are used to configure the endianess and secure 75 * timer availability for the new execution context. 76 * 77 * To prepare the register state for entry call cm_prepare_el3_exit() and 78 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 79 * cm_e1_sysreg_context_restore(). 80 ******************************************************************************/ 81 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 82 { 83 unsigned int security_state; 84 uint32_t scr_el3; 85 el3_state_t *state; 86 gp_regs_t *gp_regs; 87 unsigned long sctlr_elx; 88 89 assert(ctx); 90 91 security_state = GET_SECURITY_STATE(ep->h.attr); 92 93 /* Clear any residual register values from the context */ 94 memset(ctx, 0, sizeof(*ctx)); 95 96 /* 97 * Base the context SCR on the current value, adjust for entry point 98 * specific requirements and set trap bits from the IMF 99 * TODO: provide the base/global SCR bits using another mechanism? 100 */ 101 scr_el3 = read_scr(); 102 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 103 SCR_ST_BIT | SCR_HCE_BIT); 104 105 if (security_state != SECURE) 106 scr_el3 |= SCR_NS_BIT; 107 108 if (GET_RW(ep->spsr) == MODE_RW_64) 109 scr_el3 |= SCR_RW_BIT; 110 111 if (EP_GET_ST(ep->h.attr)) 112 scr_el3 |= SCR_ST_BIT; 113 114 #ifndef HANDLE_EA_EL3_FIRST 115 /* Explicitly stop to trap aborts from lower exception levels. */ 116 scr_el3 &= ~SCR_EA_BIT; 117 #endif 118 119 #ifdef IMAGE_BL31 120 /* 121 * IRQ/FIQ bits only need setting if interrupt routing 122 * model has been set up for BL31. 123 */ 124 scr_el3 |= get_scr_el3_from_routing_model(security_state); 125 #endif 126 127 /* 128 * Set up SCTLR_ELx for the target exception level: 129 * EE bit is taken from the entrypoint attributes 130 * M, C and I bits must be zero (as required by PSCI specification) 131 * 132 * The target exception level is based on the spsr mode requested. 133 * If execution is requested to EL2 or hyp mode, HVC is enabled 134 * via SCR_EL3.HCE. 135 * 136 * Always compute the SCTLR_EL1 value and save in the cpu_context 137 * - the EL2 registers are set up by cm_preapre_ns_entry() as they 138 * are not part of the stored cpu_context 139 * 140 * TODO: In debug builds the spsr should be validated and checked 141 * against the CPU support, security state, endianess and pc 142 */ 143 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 144 if (GET_RW(ep->spsr) == MODE_RW_64) 145 sctlr_elx |= SCTLR_EL1_RES1; 146 else { 147 sctlr_elx |= SCTLR_AARCH32_EL1_RES1; 148 /* 149 * If lower non-secure EL is AArch32, enable the CP15BEN, nTWI 150 * & nTWI bits. This aligns with SCTLR initialization on 151 * systems with an AArch32 EL3, where these bits 152 * architecturally reset to 1. 153 */ 154 if (security_state != SECURE) 155 sctlr_elx |= SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT 156 | SCTLR_NTWE_BIT; 157 } 158 159 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 160 161 if ((GET_RW(ep->spsr) == MODE_RW_64 162 && GET_EL(ep->spsr) == MODE_EL2) 163 || (GET_RW(ep->spsr) != MODE_RW_64 164 && GET_M32(ep->spsr) == MODE32_hyp)) { 165 scr_el3 |= SCR_HCE_BIT; 166 } 167 168 /* Populate EL3 state so that we've the right context before doing ERET */ 169 state = get_el3state_ctx(ctx); 170 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 171 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 172 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 173 174 /* 175 * Store the X0-X7 value from the entrypoint into the context 176 * Use memcpy as we are in control of the layout of the structures 177 */ 178 gp_regs = get_gpregs_ctx(ctx); 179 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 180 } 181 182 /******************************************************************************* 183 * The following function initializes the cpu_context for a CPU specified by 184 * its `cpu_idx` for first use, and sets the initial entrypoint state as 185 * specified by the entry_point_info structure. 186 ******************************************************************************/ 187 void cm_init_context_by_index(unsigned int cpu_idx, 188 const entry_point_info_t *ep) 189 { 190 cpu_context_t *ctx; 191 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 192 cm_init_context_common(ctx, ep); 193 } 194 195 /******************************************************************************* 196 * The following function initializes the cpu_context for the current CPU 197 * for first use, and sets the initial entrypoint state as specified by the 198 * entry_point_info structure. 199 ******************************************************************************/ 200 void cm_init_my_context(const entry_point_info_t *ep) 201 { 202 cpu_context_t *ctx; 203 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 204 cm_init_context_common(ctx, ep); 205 } 206 207 /******************************************************************************* 208 * Prepare the CPU system registers for first entry into secure or normal world 209 * 210 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 211 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 212 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 213 * For all entries, the EL1 registers are initialized from the cpu_context 214 ******************************************************************************/ 215 void cm_prepare_el3_exit(uint32_t security_state) 216 { 217 uint32_t sctlr_elx, scr_el3, cptr_el2; 218 cpu_context_t *ctx = cm_get_context(security_state); 219 220 assert(ctx); 221 222 if (security_state == NON_SECURE) { 223 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 224 if (scr_el3 & SCR_HCE_BIT) { 225 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 226 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 227 CTX_SCTLR_EL1); 228 sctlr_elx &= ~SCTLR_EE_BIT; 229 sctlr_elx |= SCTLR_EL2_RES1; 230 write_sctlr_el2(sctlr_elx); 231 } else if (read_id_aa64pfr0_el1() & 232 (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { 233 /* EL2 present but unused, need to disable safely */ 234 235 /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ 236 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 237 238 /* SCTLR_EL2 : can be ignored when bypassing */ 239 240 /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ 241 cptr_el2 = read_cptr_el2(); 242 cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); 243 write_cptr_el2(cptr_el2); 244 245 /* Enable EL1 access to timer */ 246 write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); 247 248 /* Reset CNTVOFF_EL2 */ 249 write_cntvoff_el2(0); 250 251 /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ 252 write_vpidr_el2(read_midr_el1()); 253 write_vmpidr_el2(read_mpidr_el1()); 254 255 /* 256 * Reset VTTBR_EL2. 257 * Needed because cache maintenance operations depend on 258 * the VMID even when non-secure EL1&0 stage 2 address 259 * translation are disabled. 260 */ 261 write_vttbr_el2(0); 262 /* 263 * Avoid unexpected debug traps in case where MDCR_EL2 264 * is not completely reset by the hardware - set 265 * MDCR_EL2.HPMN to PMCR_EL0.N and zero the remaining 266 * bits. 267 * MDCR_EL2.HPMN and PMCR_EL0.N fields are the same size 268 * (5 bits) and HPMN is at offset zero within MDCR_EL2. 269 */ 270 write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS) 271 >> PMCR_EL0_N_SHIFT); 272 /* 273 * Avoid unexpected traps of non-secure access to 274 * certain system registers at EL1 or lower where 275 * HSTR_EL2 is not completely reset to zero by the 276 * hardware - zero the entire register. 277 */ 278 write_hstr_el2(0); 279 /* 280 * Reset CNTHP_CTL_EL2 to disable the EL2 physical timer 281 * and therefore prevent timer interrupts. 282 */ 283 write_cnthp_ctl_el2(0); 284 } 285 } 286 287 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 288 289 cm_set_next_context(ctx); 290 } 291 292 /******************************************************************************* 293 * The next four functions are used by runtime services to save and restore 294 * EL1 context on the 'cpu_context' structure for the specified security 295 * state. 296 ******************************************************************************/ 297 void cm_el1_sysregs_context_save(uint32_t security_state) 298 { 299 cpu_context_t *ctx; 300 301 ctx = cm_get_context(security_state); 302 assert(ctx); 303 304 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 305 } 306 307 void cm_el1_sysregs_context_restore(uint32_t security_state) 308 { 309 cpu_context_t *ctx; 310 311 ctx = cm_get_context(security_state); 312 assert(ctx); 313 314 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 315 } 316 317 /******************************************************************************* 318 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 319 * given security state with the given entrypoint 320 ******************************************************************************/ 321 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 322 { 323 cpu_context_t *ctx; 324 el3_state_t *state; 325 326 ctx = cm_get_context(security_state); 327 assert(ctx); 328 329 /* Populate EL3 state so that ERET jumps to the correct entry */ 330 state = get_el3state_ctx(ctx); 331 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 332 } 333 334 /******************************************************************************* 335 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 336 * pertaining to the given security state 337 ******************************************************************************/ 338 void cm_set_elr_spsr_el3(uint32_t security_state, 339 uintptr_t entrypoint, uint32_t spsr) 340 { 341 cpu_context_t *ctx; 342 el3_state_t *state; 343 344 ctx = cm_get_context(security_state); 345 assert(ctx); 346 347 /* Populate EL3 state so that ERET jumps to the correct entry */ 348 state = get_el3state_ctx(ctx); 349 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 350 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 351 } 352 353 /******************************************************************************* 354 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 355 * pertaining to the given security state using the value and bit position 356 * specified in the parameters. It preserves all other bits. 357 ******************************************************************************/ 358 void cm_write_scr_el3_bit(uint32_t security_state, 359 uint32_t bit_pos, 360 uint32_t value) 361 { 362 cpu_context_t *ctx; 363 el3_state_t *state; 364 uint32_t scr_el3; 365 366 ctx = cm_get_context(security_state); 367 assert(ctx); 368 369 /* Ensure that the bit position is a valid one */ 370 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 371 372 /* Ensure that the 'value' is only a bit wide */ 373 assert(value <= 1); 374 375 /* 376 * Get the SCR_EL3 value from the cpu context, clear the desired bit 377 * and set it to its new value. 378 */ 379 state = get_el3state_ctx(ctx); 380 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 381 scr_el3 &= ~(1 << bit_pos); 382 scr_el3 |= value << bit_pos; 383 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 384 } 385 386 /******************************************************************************* 387 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 388 * given security state. 389 ******************************************************************************/ 390 uint32_t cm_get_scr_el3(uint32_t security_state) 391 { 392 cpu_context_t *ctx; 393 el3_state_t *state; 394 395 ctx = cm_get_context(security_state); 396 assert(ctx); 397 398 /* Populate EL3 state so that ERET jumps to the correct entry */ 399 state = get_el3state_ctx(ctx); 400 return read_ctx_reg(state, CTX_SCR_EL3); 401 } 402 403 /******************************************************************************* 404 * This function is used to program the context that's used for exception 405 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 406 * the required security state 407 ******************************************************************************/ 408 void cm_set_next_eret_context(uint32_t security_state) 409 { 410 cpu_context_t *ctx; 411 412 ctx = cm_get_context(security_state); 413 assert(ctx); 414 415 cm_set_next_context(ctx); 416 } 417