1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34#ifdef IMAGE_BL31 35#include <cpu_data.h> 36#endif 37#include <cpu_macros.S> 38#include <debug.h> 39 40 /* Reset fn is needed in BL at reset vector */ 41#if defined(IMAGE_BL1) || defined(IMAGE_BL31) 42 /* 43 * The reset handler common to all platforms. After a matching 44 * cpu_ops structure entry is found, the correponding reset_handler 45 * in the cpu_ops is invoked. 46 * Clobbers: x0 - x19, x30 47 */ 48 .globl reset_handler 49func reset_handler 50 mov x19, x30 51 52 /* The plat_reset_handler can clobber x0 - x18, x30 */ 53 bl plat_reset_handler 54 55 /* Get the matching cpu_ops pointer */ 56 bl get_cpu_ops_ptr 57#if ASM_ASSERTION 58 cmp x0, #0 59 ASM_ASSERT(ne) 60#endif 61 62 /* Get the cpu_ops reset handler */ 63 ldr x2, [x0, #CPU_RESET_FUNC] 64 mov x30, x19 65 cbz x2, 1f 66 67 /* The cpu_ops reset handler can clobber x0 - x19, x30 */ 68 br x2 691: 70 ret 71endfunc reset_handler 72 73#endif /* IMAGE_BL1 || IMAGE_BL31 */ 74 75#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ 76 /* 77 * void prepare_cpu_pwr_dwn(unsigned int power_level) 78 * 79 * Prepare CPU power down function for all platforms. The function takes 80 * a domain level to be powered down as its parameter. After the cpu_ops 81 * pointer is retrieved from cpu_data, the handler for requested power 82 * level is called. 83 */ 84 .globl prepare_cpu_pwr_dwn 85func prepare_cpu_pwr_dwn 86 /* 87 * If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the 88 * power down handler for the last power level 89 */ 90 mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1) 91 cmp x0, x2 92 csel x2, x2, x0, hi 93 94 mrs x1, tpidr_el3 95 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] 96#if ASM_ASSERTION 97 cmp x0, #0 98 ASM_ASSERT(ne) 99#endif 100 101 /* Get the appropriate power down handler */ 102 mov x1, #CPU_PWR_DWN_OPS 103 add x1, x1, x2, lsl #3 104 ldr x1, [x0, x1] 105 br x1 106endfunc prepare_cpu_pwr_dwn 107 108 109 /* 110 * Initializes the cpu_ops_ptr if not already initialized 111 * in cpu_data. This can be called without a runtime stack, but may 112 * only be called after the MMU is enabled. 113 * clobbers: x0 - x6, x10 114 */ 115 .globl init_cpu_ops 116func init_cpu_ops 117 mrs x6, tpidr_el3 118 ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] 119 cbnz x0, 1f 120 mov x10, x30 121 bl get_cpu_ops_ptr 122#if ASM_ASSERTION 123 cmp x0, #0 124 ASM_ASSERT(ne) 125#endif 126 str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! 127 mov x30, x10 1281: 129 ret 130endfunc init_cpu_ops 131#endif /* IMAGE_BL31 */ 132 133#if defined(IMAGE_BL31) && CRASH_REPORTING 134 /* 135 * The cpu specific registers which need to be reported in a crash 136 * are reported via cpu_ops cpu_reg_dump function. After a matching 137 * cpu_ops structure entry is found, the correponding cpu_reg_dump 138 * in the cpu_ops is invoked. 139 */ 140 .globl do_cpu_reg_dump 141func do_cpu_reg_dump 142 mov x16, x30 143 144 /* Get the matching cpu_ops pointer */ 145 bl get_cpu_ops_ptr 146 cbz x0, 1f 147 148 /* Get the cpu_ops cpu_reg_dump */ 149 ldr x2, [x0, #CPU_REG_DUMP] 150 cbz x2, 1f 151 blr x2 1521: 153 mov x30, x16 154 ret 155endfunc do_cpu_reg_dump 156#endif 157 158 /* 159 * The below function returns the cpu_ops structure matching the 160 * midr of the core. It reads the MIDR_EL1 and finds the matching 161 * entry in cpu_ops entries. Only the implementation and part number 162 * are used to match the entries. 163 * Return : 164 * x0 - The matching cpu_ops pointer on Success 165 * x0 - 0 on failure. 166 * Clobbers : x0 - x5 167 */ 168 .globl get_cpu_ops_ptr 169func get_cpu_ops_ptr 170 /* Get the cpu_ops start and end locations */ 171 adr x4, (__CPU_OPS_START__ + CPU_MIDR) 172 adr x5, (__CPU_OPS_END__ + CPU_MIDR) 173 174 /* Initialize the return parameter */ 175 mov x0, #0 176 177 /* Read the MIDR_EL1 */ 178 mrs x2, midr_el1 179 mov_imm x3, CPU_IMPL_PN_MASK 180 181 /* Retain only the implementation and part number using mask */ 182 and w2, w2, w3 1831: 184 /* Check if we have reached end of list */ 185 cmp x4, x5 186 b.eq error_exit 187 188 /* load the midr from the cpu_ops */ 189 ldr x1, [x4], #CPU_OPS_SIZE 190 and w1, w1, w3 191 192 /* Check if midr matches to midr of this core */ 193 cmp w1, w2 194 b.ne 1b 195 196 /* Subtract the increment and offset to get the cpu-ops pointer */ 197 sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) 198error_exit: 199 ret 200endfunc get_cpu_ops_ptr 201 202#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 203.section .rodata.rev_verbose_str, "aS" 204rev_verbose_str: 205 .asciz "VERBOSE: Skipping CPU specific reset operation for non-matching CPU revision number.\n" 206 207 /* 208 * This function prints the above warning message to the crash console. 209 * It should be called when a CPU specific operation is enabled in the 210 * build but doesn't apply to this CPU revision/part number. 211 * 212 * Clobber: x30, x0 - x5 213 */ 214 .globl print_revision_warning 215func print_revision_warning 216 mov x5, x30 217 /* Ensure the console is initialized */ 218 bl plat_crash_console_init 219 /* Check if the console is initialized */ 220 cbz x0, 1f 221 /* The console is initialized */ 222 adr x4, rev_verbose_str 223 bl asm_print_str 2241: 225 ret x5 226endfunc print_revision_warning 227#endif 228 229