fix: remove useless "return" at void functionsvoid functions() returns nothing. So remove useless "return".found using checkpatch.pl[1][1]: https://review.coreboot.org/plugins/gitiles/coreboot/
fix: remove useless "return" at void functionsvoid functions() returns nothing. So remove useless "return".found using checkpatch.pl[1][1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.plChange-Id: I3daab2abec225a657af48f7d8c215cc554713074Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
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imx: Fix multiple definition of ipc_handleThis is not conforming C and does not compile with -fno-common.Signed-off-by: Samuel Holland <samuel@sholland.org>Change-Id: I6535954cc567d6efa06919069b
imx: Fix multiple definition of ipc_handleThis is not conforming C and does not compile with -fno-common.Signed-off-by: Samuel Holland <samuel@sholland.org>Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
Update imx platform to not rely on undefined overflow behaviourThis consists of ensuring that the left operand of each shift isunsigned when the operation might overflow into the sign bit.Change
Update imx platform to not rely on undefined overflow behaviourThis consists of ensuring that the left operand of each shift isunsigned when the operation might overflow into the sign bit.Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
imx: power optimization for i.mx8qmCurrent implementation of i.MX8QM power management relatedfeatures does NOT optimize power number, all system resourceslike CCI, DDR, and A cluster etc. are kep
imx: power optimization for i.mx8qmCurrent implementation of i.MX8QM power management relatedfeatures does NOT optimize power number, all system resourceslike CCI, DDR, and A cluster etc. are kept in STBY mode (poweredON) when system suspend or CPU hotplug.To lower the power number, OFF mode should be adopted for thosesystem resources whenever they can be OFF, A cluster will be OFFif the CPUs in the cluster are all off line, DDR/MU/DB can be OFFif system suspend, IRQ steer can be OFF if the wakeup source isbelonged to system controller partition, so wakeup source runtimecheck is used to determine if IRQ steer can be OFF before systemsuspend.If resources are powered off for suspend, they should be restoredproperly after system resume.Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
imx: support for i.MX8 SoCs misc IPCNXP's i.MX8 SoCs have system controller (M4 core) which takescontrol of misc functions like temperature alarm, dma etc., otherCortex-A clusters can send out co
imx: support for i.MX8 SoCs misc IPCNXP's i.MX8 SoCs have system controller (M4 core) which takescontrol of misc functions like temperature alarm, dma etc., otherCortex-A clusters can send out command via MU (Message Unit) tosystem controller for misc operation etc..This patch adds misc IPC(inter-processor communication) support.Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Support for NXP's i.MX8 SoCs timer IPCNXP's i.MX8 SoCs have system controller (M4 core) which takescontrol of timer management, including watchdog, srtc and systemcounter etc., other clusters lik
Support for NXP's i.MX8 SoCs timer IPCNXP's i.MX8 SoCs have system controller (M4 core) which takescontrol of timer management, including watchdog, srtc and systemcounter etc., other clusters like Cortex-A35 can send out commandvia MU (Message Unit) to system controller for timer operation.This patch adds timer IPC(inter-processor communication) support.Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Sanitise includes across codebaseEnforce full include path for includes. Deprecate old paths.The following folders inside include/lib have been left unchanged:- include/lib/cpus/${ARCH}- inclu
Sanitise includes across codebaseEnforce full include path for includes. Deprecate old paths.The following folders inside include/lib have been left unchanged:- include/lib/cpus/${ARCH}- include/lib/el3_runtime/${ARCH}The reason for this change is that having a global namespace forincludes isn't a good idea. It defeats one of the advantages of havingfolders and it introduces problems that are sometimes subtle (becauseyou may not know the header you are actually including if there are twoof them).For example, this patch had to be created because two headers werecalled the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platformto avoid collision."). More recently, this patch has had similarproblems: 46f9b2c3a282 ("drivers: add tzc380 support").This problem was introduced in commit 4ecca33988b9 ("Move include andsource files to logical locations"). At that time, there weren't toomany headers so it wasn't a real issue. However, time has shown thatthis creates problems.Platforms that want to preserve the way they include headers may add theremoved paths to PLAT_INCLUDES, but this is discouraged.Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8fSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Standardise header guards across codebaseAll identifiers, regardless of use, that start with two underscores arereserved. This means they can't be used in header guards.The style that this proje
Standardise header guards across codebaseAll identifiers, regardless of use, that start with two underscores arereserved. This means they can't be used in header guards.The style that this project is now to use the full name of the file incapital letters followed by 'H'. For example, for a file called"uart_example.h", the header guard is UART_EXAMPLE_H.The exceptions are files that are imported from other projects:- CryptoCell driver- dt-bindings folders- zlib headersChange-Id: I50561bf6c88b491ec440d0c8385c74650f3c106eSigned-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
libc: Fix all includes in codebaseThe codebase was using non-standard headers. It is needed to replacethem by the correct ones so that we can use the new libc headers.Change-Id: I530f71d9510cb03
libc: Fix all includes in codebaseThe codebase was using non-standard headers. It is needed to replacethem by the correct ones so that we can use the new libc headers.Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9dAcked-by: Sumit Garg <sumit.garg@linaro.org>Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Support for NXP's i.MX8 SoCs IPCNXP's i.MX8 SoCs have system controller (M4 core)which takes control of clock management, power management,partition management, PAD management etc., othercluster
Support for NXP's i.MX8 SoCs IPCNXP's i.MX8 SoCs have system controller (M4 core)which takes control of clock management, power management,partition management, PAD management etc., otherclusters like Cortex-A35 can send out command via MU(Message Unit) to system controller for clock/powermanagement etc..This patch adds basic IPC(inter-processor communication) support.Signed-off-by: Anson Huang <Anson.Huang@nxp.com>