1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <denver.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 18 #include <mce.h> 19 #include <memctrl.h> 20 #include <t18x_ari.h> 21 #include <tegra_private.h> 22 23 /******************************************************************************* 24 * Offset to read the ref_clk counter value 25 ******************************************************************************/ 26 #define REF_CLK_OFFSET 4 27 28 /******************************************************************************* 29 * Tegra186 SiP SMCs 30 ******************************************************************************/ 31 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 32 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 33 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 34 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 35 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 36 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 37 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 38 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 39 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 40 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 41 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 42 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A 43 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B 44 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C 45 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D 46 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E 47 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F 48 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 49 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 50 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 51 52 /******************************************************************************* 53 * This function is responsible for handling all T186 SiP calls 54 ******************************************************************************/ 55 int plat_sip_handler(uint32_t smc_fid, 56 uint64_t x1, 57 uint64_t x2, 58 uint64_t x3, 59 uint64_t x4, 60 const void *cookie, 61 void *handle, 62 uint64_t flags) 63 { 64 int mce_ret; 65 int impl, cpu; 66 uint32_t base, core_clk_ctr, ref_clk_ctr; 67 68 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 69 /* 32-bit function, clear top parameter bits */ 70 71 x1 = (uint32_t)x1; 72 x2 = (uint32_t)x2; 73 x3 = (uint32_t)x3; 74 } 75 76 /* 77 * Convert SMC FID to SMC64, to support SMC32/SMC64 configurations 78 */ 79 smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); 80 81 switch (smc_fid) { 82 /* 83 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 84 * 0x82FFFFFF SiP SMC space 85 */ 86 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 87 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 88 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 89 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 90 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 91 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 92 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 93 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 94 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 95 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 96 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 97 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 98 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 99 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 100 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 101 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 102 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 103 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 104 105 /* clean up the high bits */ 106 smc_fid &= MCE_CMD_MASK; 107 108 /* execute the command and store the result */ 109 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 110 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, 111 (uint64_t)mce_ret); 112 113 return 0; 114 115 /* 116 * This function ID reads the Activity monitor's core/ref clock 117 * counter values for a core/cluster. 118 * 119 * x1 = MPIDR of the target core 120 * x2 = MIDR of the target core 121 */ 122 case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS: 123 124 cpu = (uint32_t)x1 & MPIDR_CPU_MASK; 125 impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 126 127 /* sanity check target CPU number */ 128 if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER) 129 return -EINVAL; 130 131 /* get the base address for the current CPU */ 132 base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE : 133 TEGRA_ARM_ACTMON_CTR_BASE; 134 135 /* read the clock counter values */ 136 core_clk_ctr = mmio_read_32(base + (8 * cpu)); 137 ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET); 138 139 /* return the counter values as two different parameters */ 140 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, 141 (uint64_t)core_clk_ctr); 142 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, 143 (uint64_t)ref_clk_ctr); 144 145 return 0; 146 147 default: 148 break; 149 } 150 151 return -ENOTSUP; 152 } 153