1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10 11 12 .globl bl2_entrypoint 13 14 15 16func bl2_entrypoint 17 /*--------------------------------------------- 18 * Save arguments x0 - x3 from BL1 for future 19 * use. 20 * --------------------------------------------- 21 */ 22 mov x20, x0 23 mov x21, x1 24 mov x22, x2 25 mov x23, x3 26 27 /* --------------------------------------------- 28 * Set the exception vector to something sane. 29 * --------------------------------------------- 30 */ 31 adr x0, early_exceptions 32 msr vbar_el1, x0 33 isb 34 35 /* --------------------------------------------- 36 * Enable the SError interrupt now that the 37 * exception vectors have been setup. 38 * --------------------------------------------- 39 */ 40 msr daifclr, #DAIF_ABT_BIT 41 42 /* --------------------------------------------- 43 * Enable the instruction cache, stack pointer 44 * and data access alignment checks 45 * --------------------------------------------- 46 */ 47 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 48 mrs x0, sctlr_el1 49 orr x0, x0, x1 50 msr sctlr_el1, x0 51 isb 52 53 /* --------------------------------------------- 54 * Invalidate the RW memory used by the BL2 55 * image. This includes the data and NOBITS 56 * sections. This is done to safeguard against 57 * possible corruption of this memory by dirty 58 * cache lines in a system cache as a result of 59 * use by an earlier boot loader stage. 60 * --------------------------------------------- 61 */ 62 adr x0, __RW_START__ 63 adr x1, __RW_END__ 64 sub x1, x1, x0 65 bl inv_dcache_range 66 67 /* --------------------------------------------- 68 * Zero out NOBITS sections. There are 2 of them: 69 * - the .bss section; 70 * - the coherent memory section. 71 * --------------------------------------------- 72 */ 73 ldr x0, =__BSS_START__ 74 ldr x1, =__BSS_SIZE__ 75 bl zeromem 76 77#if USE_COHERENT_MEM 78 ldr x0, =__COHERENT_RAM_START__ 79 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 80 bl zeromem 81#endif 82 83 /* -------------------------------------------- 84 * Allocate a stack whose memory will be marked 85 * as Normal-IS-WBWA when the MMU is enabled. 86 * There is no risk of reading stale stack 87 * memory after enabling the MMU as only the 88 * primary cpu is running at the moment. 89 * -------------------------------------------- 90 */ 91 bl plat_set_my_stack 92 93 /* --------------------------------------------- 94 * Initialize the stack protector canary before 95 * any C code is called. 96 * --------------------------------------------- 97 */ 98#if STACK_PROTECTOR_ENABLED 99 bl update_stack_protector_canary 100#endif 101 102 /* --------------------------------------------- 103 * Perform early platform setup & platform 104 * specific early arch. setup e.g. mmu setup 105 * --------------------------------------------- 106 */ 107 mov x0, x20 108 mov x1, x21 109 mov x2, x22 110 mov x3, x23 111 bl bl2_early_platform_setup2 112 113 bl bl2_plat_arch_setup 114 115 /* --------------------------------------------- 116 * Jump to main function. 117 * --------------------------------------------- 118 */ 119 bl bl2_main 120 121 /* --------------------------------------------- 122 * Should never reach this point. 123 * --------------------------------------------- 124 */ 125 no_ret plat_panic_handler 126 127endfunc bl2_entrypoint 128