1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SE_PRIVATE_H 9 #define SE_PRIVATE_H 10 11 #include <stdbool.h> 12 #include <security_engine.h> 13 14 /* 15 * PMC registers 16 */ 17 18 /* Secure scratch registers */ 19 #define PMC_SECURE_SCRATCH4_OFFSET 0xC0U 20 #define PMC_SECURE_SCRATCH5_OFFSET 0xC4U 21 #define PMC_SECURE_SCRATCH6_OFFSET 0x224U 22 #define PMC_SECURE_SCRATCH7_OFFSET 0x228U 23 #define PMC_SECURE_SCRATCH120_OFFSET 0xB38U 24 #define PMC_SECURE_SCRATCH121_OFFSET 0xB3CU 25 #define PMC_SECURE_SCRATCH122_OFFSET 0xB40U 26 #define PMC_SECURE_SCRATCH123_OFFSET 0xB44U 27 28 /* 29 * AHB arbitration memory write queue 30 */ 31 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU 32 #define ARAHB_MST_ID_SE2_MASK (0x1U << 13) 33 #define ARAHB_MST_ID_SE_MASK (0x1U << 14) 34 35 /* SE Status register */ 36 #define SE_STATUS_OFFSET 0x800U 37 #define SE_STATUS_SHIFT 0 38 #define SE_STATUS_IDLE \ 39 ((0U) << SE_STATUS_SHIFT) 40 #define SE_STATUS_BUSY \ 41 ((1U) << SE_STATUS_SHIFT) 42 #define SE_STATUS(x) \ 43 ((x) & ((0x3U) << SE_STATUS_SHIFT)) 44 45 /* SE config register */ 46 #define SE_CONFIG_REG_OFFSET 0x14U 47 #define SE_CONFIG_ENC_ALG_SHIFT 12 48 #define SE_CONFIG_ENC_ALG_AES_ENC \ 49 ((1U) << SE_CONFIG_ENC_ALG_SHIFT) 50 #define SE_CONFIG_ENC_ALG_RNG \ 51 ((2U) << SE_CONFIG_ENC_ALG_SHIFT) 52 #define SE_CONFIG_ENC_ALG_SHA \ 53 ((3U) << SE_CONFIG_ENC_ALG_SHIFT) 54 #define SE_CONFIG_ENC_ALG_RSA \ 55 ((4U) << SE_CONFIG_ENC_ALG_SHIFT) 56 #define SE_CONFIG_ENC_ALG_NOP \ 57 ((0U) << SE_CONFIG_ENC_ALG_SHIFT) 58 #define SE_CONFIG_ENC_ALG(x) \ 59 ((x) & ((0xFU) << SE_CONFIG_ENC_ALG_SHIFT)) 60 61 #define SE_CONFIG_DEC_ALG_SHIFT 8 62 #define SE_CONFIG_DEC_ALG_AES \ 63 ((1U) << SE_CONFIG_DEC_ALG_SHIFT) 64 #define SE_CONFIG_DEC_ALG_NOP \ 65 ((0U) << SE_CONFIG_DEC_ALG_SHIFT) 66 #define SE_CONFIG_DEC_ALG(x) \ 67 ((x) & ((0xFU) << SE_CONFIG_DEC_ALG_SHIFT)) 68 69 #define SE_CONFIG_DST_SHIFT 2 70 #define SE_CONFIG_DST_MEMORY \ 71 ((0U) << SE_CONFIG_DST_SHIFT) 72 #define SE_CONFIG_DST_HASHREG \ 73 ((1U) << SE_CONFIG_DST_SHIFT) 74 #define SE_CONFIG_DST_KEYTAB \ 75 ((2U) << SE_CONFIG_DST_SHIFT) 76 #define SE_CONFIG_DST_SRK \ 77 ((3U) << SE_CONFIG_DST_SHIFT) 78 #define SE_CONFIG_DST_RSAREG \ 79 ((4U) << SE_CONFIG_DST_SHIFT) 80 #define SE_CONFIG_DST(x) \ 81 ((x) & ((0x7U) << SE_CONFIG_DST_SHIFT)) 82 83 /* DRBG random number generator config */ 84 #define SE_RNG_CONFIG_REG_OFFSET 0x340 85 86 #define DRBG_MODE_SHIFT 0 87 #define DRBG_MODE_NORMAL \ 88 ((0UL) << DRBG_MODE_SHIFT) 89 #define DRBG_MODE_FORCE_INSTANTION \ 90 ((1UL) << DRBG_MODE_SHIFT) 91 #define DRBG_MODE_FORCE_RESEED \ 92 ((2UL) << DRBG_MODE_SHIFT) 93 #define SE_RNG_CONFIG_MODE(x) \ 94 ((x) & ((0x3UL) << DRBG_MODE_SHIFT)) 95 96 #define DRBG_SRC_SHIFT 2 97 #define DRBG_SRC_NONE \ 98 ((0UL) << DRBG_SRC_SHIFT) 99 #define DRBG_SRC_ENTROPY \ 100 ((1UL) << DRBG_SRC_SHIFT) 101 #define DRBG_SRC_LFSR \ 102 ((2UL) << DRBG_SRC_SHIFT) 103 #define SE_RNG_SRC_CONFIG_MODE(x) \ 104 ((x) & ((0x3UL) << DRBG_SRC_SHIFT)) 105 106 /* DRBG random number generator entropy config */ 107 #define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U 108 109 #define DRBG_RO_ENT_SRC_SHIFT 1 110 #define DRBG_RO_ENT_SRC_ENABLE \ 111 ((1U) << DRBG_RO_ENT_SRC_SHIFT) 112 #define DRBG_RO_ENT_SRC_DISABLE \ 113 ((0U) << DRBG_RO_ENT_SRC_SHIFT) 114 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC(x) \ 115 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_SHIFT)) 116 117 #define DRBG_RO_ENT_SRC_LOCK_SHIFT 0 118 #define DRBG_RO_ENT_SRC_LOCK_ENABLE \ 119 ((1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 120 #define DRBG_RO_ENT_SRC_LOCK_DISABLE \ 121 ((0U) << DRBG_RO_ENT_SRC_LOCK_SHIFT) 122 #define SE_RNG_SRC_CONFIG_RO_ENT_SRC_LOCK(x) \ 123 ((x) & ((0x1U) << DRBG_RO_ENT_SRC_LOCK_SHIFT)) 124 125 #define DRBG_RO_ENT_IGNORE_MEM_SHIFT 12 126 #define DRBG_RO_ENT_IGNORE_MEM_ENABLE \ 127 ((1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 128 #define DRBG_RO_ENT_IGNORE_MEM_DISABLE \ 129 ((0U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT) 130 #define SE_RNG_SRC_CONFIG_RO_ENT_IGNORE_MEM(x) \ 131 ((x) & ((0x1U) << DRBG_RO_ENT_IGNORE_MEM_SHIFT)) 132 133 /* SE OPERATION */ 134 #define SE_OPERATION_REG_OFFSET 0x8U 135 #define SE_OPERATION_SHIFT 0 136 #define SE_OP_ABORT \ 137 ((0x0U) << SE_OPERATION_SHIFT) 138 #define SE_OP_START \ 139 ((0x1U) << SE_OPERATION_SHIFT) 140 #define SE_OP_RESTART \ 141 ((0x2U) << SE_OPERATION_SHIFT) 142 #define SE_OP_CTX_SAVE \ 143 ((0x3U) << SE_OPERATION_SHIFT) 144 #define SE_OP_RESTART_IN \ 145 ((0x4U) << SE_OPERATION_SHIFT) 146 #define SE_OPERATION(x) \ 147 ((x) & ((0x7U) << SE_OPERATION_SHIFT)) 148 149 /* SE_CTX_SAVE_AUTO */ 150 #define SE_CTX_SAVE_AUTO_REG_OFFSET 0x74U 151 152 /* Enable */ 153 #define SE_CTX_SAVE_AUTO_ENABLE_SHIFT 0 154 #define SE_CTX_SAVE_AUTO_DIS \ 155 ((0U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 156 #define SE_CTX_SAVE_AUTO_EN \ 157 ((1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT) 158 #define SE_CTX_SAVE_AUTO_ENABLE(x) \ 159 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_ENABLE_SHIFT)) 160 161 /* Lock */ 162 #define SE_CTX_SAVE_AUTO_LOCK_SHIFT 8 163 #define SE_CTX_SAVE_AUTO_LOCK_EN \ 164 ((1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 165 #define SE_CTX_SAVE_AUTO_LOCK_DIS \ 166 ((0U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT) 167 #define SE_CTX_SAVE_AUTO_LOCK(x) \ 168 ((x) & ((0x1U) << SE_CTX_SAVE_AUTO_LOCK_SHIFT)) 169 170 /* Current context save number of blocks */ 171 #define SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT 16 172 #define SE_CTX_SAVE_AUTO_CURR_CNT_MASK 0x3FFU 173 #define SE_CTX_SAVE_GET_BLK_COUNT(x) \ 174 (((x) >> SE_CTX_SAVE_AUTO_CURR_CNT_SHIFT) & \ 175 SE_CTX_SAVE_AUTO_CURR_CNT_MASK) 176 177 #define SE_CTX_SAVE_SIZE_BLOCKS_SE1 133 178 #define SE_CTX_SAVE_SIZE_BLOCKS_SE2 646 179 180 /* SE TZRAM OPERATION - only for SE1 */ 181 #define SE_TZRAM_OPERATION 0x540U 182 183 #define SE_TZRAM_OP_MODE_SHIFT 1 184 #define SE_TZRAM_OP_MODE_SAVE \ 185 ((0U) << SE_TZRAM_OP_MODE_SHIFT) 186 #define SE_TZRAM_OP_MODE_RESTORE \ 187 ((1U) << SE_TZRAM_OP_MODE_SHIFT) 188 #define SE_TZRAM_OP_MODE(x) \ 189 ((x) & ((0x1U) << SE_TZRAM_OP_MODE_SHIFT)) 190 191 #define SE_TZRAM_OP_BUSY_SHIFT 2 192 #define SE_TZRAM_OP_BUSY_OFF \ 193 ((0U) << SE_TZRAM_OP_BUSY_SHIFT) 194 #define SE_TZRAM_OP_BUSY_ON \ 195 ((1U) << SE_TZRAM_OP_BUSY_SHIFT) 196 #define SE_TZRAM_OP_BUSY(x) \ 197 ((x) & ((0x1U) << SE_TZRAM_OP_BUSY_SHIFT)) 198 199 #define SE_TZRAM_OP_REQ_SHIFT 0 200 #define SE_TZRAM_OP_REQ_IDLE \ 201 ((0U) << SE_TZRAM_OP_REQ_SHIFT) 202 #define SE_TZRAM_OP_REQ_INIT \ 203 ((1U) << SE_TZRAM_OP_REQ_SHIFT) 204 #define SE_TZRAM_OP_REQ(x) \ 205 ((x) & ((0x1U) << SE_TZRAM_OP_REQ_SHIFT)) 206 207 /* SE Interrupt */ 208 #define SE_INT_STATUS_REG_OFFSET 0x10U 209 #define SE_INT_OP_DONE_SHIFT 4 210 #define SE_INT_OP_DONE_CLEAR \ 211 ((0U) << SE_INT_OP_DONE_SHIFT) 212 #define SE_INT_OP_DONE_ACTIVE \ 213 ((1U) << SE_INT_OP_DONE_SHIFT) 214 #define SE_INT_OP_DONE(x) \ 215 ((x) & ((0x1U) << SE_INT_OP_DONE_SHIFT)) 216 217 /* SE error status */ 218 #define SE_ERR_STATUS_REG_OFFSET 0x804U 219 220 /* SE linked list (LL) register */ 221 #define SE_IN_LL_ADDR_REG_OFFSET 0x18U 222 #define SE_OUT_LL_ADDR_REG_OFFSET 0x24U 223 #define SE_BLOCK_COUNT_REG_OFFSET 0x318U 224 225 /* AES data sizes */ 226 #define TEGRA_SE_AES_BLOCK_SIZE 16 227 #define TEGRA_SE_AES_MIN_KEY_SIZE 16 228 #define TEGRA_SE_AES_MAX_KEY_SIZE 32 229 #define TEGRA_SE_AES_IV_SIZE 16 230 231 /******************************************************************************* 232 * Inline functions definition 233 ******************************************************************************/ 234 235 static inline uint32_t tegra_se_read_32(const tegra_se_dev_t *dev, uint32_t offset) 236 { 237 return mmio_read_32(dev->se_base + offset); 238 } 239 240 static inline void tegra_se_write_32(const tegra_se_dev_t *dev, uint32_t offset, uint32_t val) 241 { 242 mmio_write_32(dev->se_base + offset, val); 243 } 244 245 /******************************************************************************* 246 * Prototypes 247 ******************************************************************************/ 248 249 #endif /* SE_PRIVATE_H */ 250