1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <console.h> 7 #include <generic_delay_timer.h> 8 #include <plat_arm.h> 9 #include <platform.h> 10 11 #pragma weak bl2_el3_early_platform_setup 12 #pragma weak bl2_el3_plat_arch_setup 13 #pragma weak bl2_el3_plat_prepare_exit 14 15 static meminfo_t bl2_el3_tzram_layout; 16 17 /* 18 * Perform arm specific early platform setup. At this moment we only initialize 19 * the console and the memory layout. 20 */ 21 void arm_bl2_el3_early_platform_setup(void) 22 { 23 /* Initialize the console to provide early debug support */ 24 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 25 ARM_CONSOLE_BAUDRATE); 26 27 /* 28 * Allow BL2 to see the whole Trusted RAM. This is determined 29 * statically since we cannot rely on BL1 passing this information 30 * in the BL2_AT_EL3 case. 31 */ 32 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE; 33 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE; 34 35 /* Initialise the IO layer and register platform IO devices */ 36 plat_arm_io_setup(); 37 } 38 39 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 40 u_register_t arg1 __unused, 41 u_register_t arg2 __unused, 42 u_register_t arg3 __unused) 43 { 44 arm_bl2_el3_early_platform_setup(); 45 46 /* 47 * Initialize Interconnect for this cluster during cold boot. 48 * No need for locks as no other CPU is active. 49 */ 50 plat_arm_interconnect_init(); 51 /* 52 * Enable Interconnect coherency for the primary CPU's cluster. 53 */ 54 plat_arm_interconnect_enter_coherency(); 55 56 generic_delay_timer_init(); 57 } 58 59 /******************************************************************************* 60 * Perform the very early platform specific architectural setup here. At the 61 * moment this is only initializes the mmu in a quick and dirty way. 62 ******************************************************************************/ 63 void arm_bl2_el3_plat_arch_setup(void) 64 { 65 arm_setup_page_tables(bl2_el3_tzram_layout.total_base, 66 bl2_el3_tzram_layout.total_size, 67 BL_CODE_BASE, 68 BL_CODE_END, 69 BL_RO_DATA_BASE, 70 BL_RO_DATA_END 71 #if USE_COHERENT_MEM 72 , BL_COHERENT_RAM_BASE, 73 BL_COHERENT_RAM_END 74 #endif 75 ); 76 77 #ifdef AARCH32 78 enable_mmu_secure(0); 79 #else 80 enable_mmu_el3(0); 81 #endif 82 } 83 84 void bl2_el3_plat_arch_setup(void) 85 { 86 arm_bl2_el3_plat_arch_setup(); 87 } 88 89 void bl2_el3_plat_prepare_exit(void) 90 { 91 } 92