1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <assert.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <stdint.h> 13 14 #define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo) 15 #define CCI_PART_LO_MASK 0xff 16 #define CCI_PART_HI_MASK 0xf 17 18 /* CCI part number codes read from Peripheral ID registers 0 and 1 */ 19 #define CCI400_PART_NUM 0x420 20 #define CCI500_PART_NUM 0x422 21 #define CCI550_PART_NUM 0x423 22 23 #define CCI400_SLAVE_PORTS 5 24 #define CCI500_SLAVE_PORTS 7 25 #define CCI550_SLAVE_PORTS 7 26 27 static uintptr_t cci_base; 28 static const int *cci_slave_if_map; 29 30 #if ENABLE_ASSERTIONS 31 static unsigned int max_master_id; 32 static int cci_num_slave_ports; 33 34 static int validate_cci_map(const int *map) 35 { 36 unsigned int valid_cci_map = 0; 37 int slave_if_id; 38 int i; 39 40 /* Validate the map */ 41 for (i = 0; i <= max_master_id; i++) { 42 slave_if_id = map[i]; 43 44 if (slave_if_id < 0) 45 continue; 46 47 if (slave_if_id >= cci_num_slave_ports) { 48 ERROR("Slave interface ID is invalid\n"); 49 return 0; 50 } 51 52 if (valid_cci_map & (1 << slave_if_id)) { 53 ERROR("Multiple masters are assigned same slave interface ID\n"); 54 return 0; 55 } 56 valid_cci_map |= 1 << slave_if_id; 57 } 58 59 if (!valid_cci_map) { 60 ERROR("No master is assigned a valid slave interface\n"); 61 return 0; 62 } 63 64 return 1; 65 } 66 67 /* 68 * Read CCI part number from Peripheral ID registers 69 */ 70 static unsigned int read_cci_part_number(uintptr_t base) 71 { 72 unsigned int part_lo, part_hi; 73 74 part_lo = mmio_read_32(base + PERIPHERAL_ID0) & CCI_PART_LO_MASK; 75 part_hi = mmio_read_32(base + PERIPHERAL_ID1) & CCI_PART_HI_MASK; 76 77 return MAKE_CCI_PART_NUMBER(part_hi, part_lo); 78 } 79 80 /* 81 * Identify a CCI device, and return the number of slaves. Return -1 for an 82 * unidentified device. 83 */ 84 static int get_slave_ports(unsigned int part_num) 85 { 86 int num_slave_ports = -1; 87 88 switch (part_num) { 89 90 case CCI400_PART_NUM: 91 num_slave_ports = CCI400_SLAVE_PORTS; 92 break; 93 case CCI500_PART_NUM: 94 num_slave_ports = CCI500_SLAVE_PORTS; 95 break; 96 case CCI550_PART_NUM: 97 num_slave_ports = CCI550_SLAVE_PORTS; 98 break; 99 default: 100 /* Do nothing in default case */ 101 break; 102 } 103 104 return num_slave_ports; 105 } 106 #endif /* ENABLE_ASSERTIONS */ 107 108 void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters) 109 { 110 assert(map); 111 assert(base); 112 113 cci_base = base; 114 cci_slave_if_map = map; 115 116 #if ENABLE_ASSERTIONS 117 /* 118 * Master Id's are assigned from zero, So in an array of size n 119 * the max master id is (n - 1). 120 */ 121 max_master_id = num_cci_masters - 1; 122 cci_num_slave_ports = get_slave_ports(read_cci_part_number(base)); 123 #endif 124 assert(cci_num_slave_ports >= 0); 125 126 assert(validate_cci_map(map)); 127 } 128 129 void cci_enable_snoop_dvm_reqs(unsigned int master_id) 130 { 131 int slave_if_id = cci_slave_if_map[master_id]; 132 133 assert(master_id <= max_master_id); 134 assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); 135 assert(cci_base); 136 137 /* 138 * Enable Snoops and DVM messages, no need for Read/Modify/Write as 139 * rest of bits are write ignore 140 */ 141 mmio_write_32(cci_base + 142 SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG, 143 DVM_EN_BIT | SNOOP_EN_BIT); 144 145 /* Wait for the dust to settle down */ 146 while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) 147 ; 148 } 149 150 void cci_disable_snoop_dvm_reqs(unsigned int master_id) 151 { 152 int slave_if_id = cci_slave_if_map[master_id]; 153 154 assert(master_id <= max_master_id); 155 assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); 156 assert(cci_base); 157 158 /* 159 * Disable Snoops and DVM messages, no need for Read/Modify/Write as 160 * rest of bits are write ignore. 161 */ 162 mmio_write_32(cci_base + 163 SLAVE_IFACE_OFFSET(slave_if_id) + SNOOP_CTRL_REG, 164 ~(DVM_EN_BIT | SNOOP_EN_BIT)); 165 166 /* Wait for the dust to settle down */ 167 while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) 168 ; 169 } 170 171