1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100func check_errata_cve_2017_5715 101 cpu_check_csv2 x0, 1f 102#if WORKAROUND_CVE_2017_5715 103 mov x0, #ERRATA_APPLIES 104#else 105 mov x0, #ERRATA_MISSING 106#endif 107 ret 1081: 109 mov x0, #ERRATA_NOT_APPLIES 110 ret 111endfunc check_errata_cve_2017_5715 112 113func check_errata_cve_2018_3639 114#if WORKAROUND_CVE_2018_3639 115 mov x0, #ERRATA_APPLIES 116#else 117 mov x0, #ERRATA_MISSING 118#endif 119 ret 120endfunc check_errata_cve_2018_3639 121 122 /* ------------------------------------------------- 123 * The CPU Ops reset function for Cortex-A72. 124 * ------------------------------------------------- 125 */ 126func cortex_a72_reset_func 127 mov x19, x30 128 bl cpu_get_rev_var 129 mov x18, x0 130 131#if ERRATA_A72_859971 132 mov x0, x18 133 bl errata_a72_859971_wa 134#endif 135 136#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 137 cpu_check_csv2 x0, 1f 138 adr x0, wa_cve_2017_5715_mmu_vbar 139 msr vbar_el3, x0 1401: 141#endif 142 143#if WORKAROUND_CVE_2018_3639 144 mrs x0, CORTEX_A72_CPUACTLR_EL1 145 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 146 msr CORTEX_A72_CPUACTLR_EL1, x0 147 isb 148 dsb sy 149#endif 150 151 /* --------------------------------------------- 152 * Enable the SMP bit. 153 * --------------------------------------------- 154 */ 155 mrs x0, CORTEX_A72_ECTLR_EL1 156 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 157 msr CORTEX_A72_ECTLR_EL1, x0 158 isb 159 ret x19 160endfunc cortex_a72_reset_func 161 162 /* ---------------------------------------------------- 163 * The CPU Ops core power down function for Cortex-A72. 164 * ---------------------------------------------------- 165 */ 166func cortex_a72_core_pwr_dwn 167 mov x18, x30 168 169 /* --------------------------------------------- 170 * Turn off caches. 171 * --------------------------------------------- 172 */ 173 bl cortex_a72_disable_dcache 174 175 /* --------------------------------------------- 176 * Disable the L2 prefetches. 177 * --------------------------------------------- 178 */ 179 bl cortex_a72_disable_l2_prefetch 180 181 /* --------------------------------------------- 182 * Disable the load-store hardware prefetcher. 183 * --------------------------------------------- 184 */ 185 bl cortex_a72_disable_hw_prefetcher 186 187 /* --------------------------------------------- 188 * Flush L1 caches. 189 * --------------------------------------------- 190 */ 191 mov x0, #DCCISW 192 bl dcsw_op_level1 193 194 /* --------------------------------------------- 195 * Come out of intra cluster coherency 196 * --------------------------------------------- 197 */ 198 bl cortex_a72_disable_smp 199 200 /* --------------------------------------------- 201 * Force the debug interfaces to be quiescent 202 * --------------------------------------------- 203 */ 204 mov x30, x18 205 b cortex_a72_disable_ext_debug 206endfunc cortex_a72_core_pwr_dwn 207 208 /* ------------------------------------------------------- 209 * The CPU Ops cluster power down function for Cortex-A72. 210 * ------------------------------------------------------- 211 */ 212func cortex_a72_cluster_pwr_dwn 213 mov x18, x30 214 215 /* --------------------------------------------- 216 * Turn off caches. 217 * --------------------------------------------- 218 */ 219 bl cortex_a72_disable_dcache 220 221 /* --------------------------------------------- 222 * Disable the L2 prefetches. 223 * --------------------------------------------- 224 */ 225 bl cortex_a72_disable_l2_prefetch 226 227 /* --------------------------------------------- 228 * Disable the load-store hardware prefetcher. 229 * --------------------------------------------- 230 */ 231 bl cortex_a72_disable_hw_prefetcher 232 233#if !SKIP_A72_L1_FLUSH_PWR_DWN 234 /* --------------------------------------------- 235 * Flush L1 caches. 236 * --------------------------------------------- 237 */ 238 mov x0, #DCCISW 239 bl dcsw_op_level1 240#endif 241 242 /* --------------------------------------------- 243 * Disable the optional ACP. 244 * --------------------------------------------- 245 */ 246 bl plat_disable_acp 247 248 /* ------------------------------------------------- 249 * Flush the L2 caches. 250 * ------------------------------------------------- 251 */ 252 mov x0, #DCCISW 253 bl dcsw_op_level2 254 255 /* --------------------------------------------- 256 * Come out of intra cluster coherency 257 * --------------------------------------------- 258 */ 259 bl cortex_a72_disable_smp 260 261 /* --------------------------------------------- 262 * Force the debug interfaces to be quiescent 263 * --------------------------------------------- 264 */ 265 mov x30, x18 266 b cortex_a72_disable_ext_debug 267endfunc cortex_a72_cluster_pwr_dwn 268 269#if REPORT_ERRATA 270/* 271 * Errata printing function for Cortex A72. Must follow AAPCS. 272 */ 273func cortex_a72_errata_report 274 stp x8, x30, [sp, #-16]! 275 276 bl cpu_get_rev_var 277 mov x8, x0 278 279 /* 280 * Report all errata. The revision-variant information is passed to 281 * checking functions of each errata. 282 */ 283 report_errata ERRATA_A72_859971, cortex_a72, 859971 284 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 285 report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 286 287 ldp x8, x30, [sp], #16 288 ret 289endfunc cortex_a72_errata_report 290#endif 291 292 /* --------------------------------------------- 293 * This function provides cortex_a72 specific 294 * register information for crash reporting. 295 * It needs to return with x6 pointing to 296 * a list of register names in ascii and 297 * x8 - x15 having values of registers to be 298 * reported. 299 * --------------------------------------------- 300 */ 301.section .rodata.cortex_a72_regs, "aS" 302cortex_a72_regs: /* The ascii list of register names to be reported */ 303 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 304 305func cortex_a72_cpu_reg_dump 306 adr x6, cortex_a72_regs 307 mrs x8, CORTEX_A72_ECTLR_EL1 308 mrs x9, CORTEX_A72_MERRSR_EL1 309 mrs x10, CORTEX_A72_L2MERRSR_EL1 310 ret 311endfunc cortex_a72_cpu_reg_dump 312 313declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 314 cortex_a72_reset_func, \ 315 check_errata_cve_2017_5715, \ 316 CPU_NO_EXTRA2_FUNC, \ 317 cortex_a72_core_pwr_dwn, \ 318 cortex_a72_cluster_pwr_dwn 319