1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_config.h> 9 #include <cassert.h> 10 #include <plat_arm.h> 11 #include <platform.h> 12 #include <platform_def.h> 13 #include "drivers/pwrc/fvp_pwrc.h" 14 15 /* The FVP power domain tree descriptor */ 16 static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2]; 17 18 19 CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count); 20 21 /******************************************************************************* 22 * This function dynamically constructs the topology according to 23 * FVP_CLUSTER_COUNT and returns it. 24 ******************************************************************************/ 25 const unsigned char *plat_get_power_domain_tree_desc(void) 26 { 27 unsigned int i; 28 29 /* 30 * The highest level is the system level. The next level is constituted 31 * by clusters and then cores in clusters. 32 */ 33 fvp_power_domain_tree_desc[0] = 1; 34 fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT; 35 36 for (i = 0; i < FVP_CLUSTER_COUNT; i++) 37 fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER; 38 39 40 return fvp_power_domain_tree_desc; 41 } 42 43 /******************************************************************************* 44 * This function returns the core count within the cluster corresponding to 45 * `mpidr`. 46 ******************************************************************************/ 47 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 48 { 49 return FVP_MAX_CPUS_PER_CLUSTER; 50 } 51 52 /******************************************************************************* 53 * This function implements a part of the critical interface between the psci 54 * generic layer and the platform that allows the former to query the platform 55 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 56 * in case the MPIDR is invalid. 57 ******************************************************************************/ 58 int plat_core_pos_by_mpidr(u_register_t mpidr) 59 { 60 unsigned int clus_id, cpu_id, thread_id; 61 62 /* Validate affinity fields */ 63 if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) { 64 thread_id = MPIDR_AFFLVL0_VAL(mpidr); 65 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 66 clus_id = MPIDR_AFFLVL2_VAL(mpidr); 67 } else { 68 thread_id = 0; 69 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 70 clus_id = MPIDR_AFFLVL1_VAL(mpidr); 71 } 72 73 if (clus_id >= FVP_CLUSTER_COUNT) 74 return -1; 75 if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER) 76 return -1; 77 if (thread_id >= FVP_MAX_PE_PER_CPU) 78 return -1; 79 80 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) 81 return -1; 82 83 /* 84 * Core position calculation for FVP platform depends on the MT bit in 85 * MPIDR. This function cannot assume that the supplied MPIDR has the MT 86 * bit set even if the implementation has. For example, PSCI clients 87 * might supply MPIDR values without the MT bit set. Therefore, we 88 * inject the current PE's MT bit so as to get the calculation correct. 89 * This of course assumes that none or all CPUs on the platform has MT 90 * bit set. 91 */ 92 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 93 return plat_arm_calc_core_pos(mpidr); 94 } 95