1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <bl_common.h> 9 #include <console.h> 10 #include <tegra_def.h> 11 #include <tegra_private.h> 12 #include <xlat_tables_v2.h> 13 14 /******************************************************************************* 15 * The Tegra power domain tree has a single system level power domain i.e. a 16 * single root node. The first entry in the power domain descriptor specifies 17 * the number of power domains at the highest power level. 18 ******************************************************************************* 19 */ 20 const unsigned char tegra_power_domain_tree_desc[] = { 21 /* No of root nodes */ 22 1, 23 /* No of clusters */ 24 PLATFORM_CLUSTER_COUNT, 25 /* No of CPU cores - cluster0 */ 26 PLATFORM_MAX_CPUS_PER_CLUSTER, 27 /* No of CPU cores - cluster1 */ 28 PLATFORM_MAX_CPUS_PER_CLUSTER 29 }; 30 31 /* sets of MMIO ranges setup */ 32 #define MMIO_RANGE_0_ADDR 0x50000000 33 #define MMIO_RANGE_1_ADDR 0x60000000 34 #define MMIO_RANGE_2_ADDR 0x70000000 35 #define MMIO_RANGE_SIZE 0x200000 36 37 /* 38 * Table of regions to map using the MMU. 39 */ 40 static const mmap_region_t tegra_mmap[] = { 41 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 46 MT_DEVICE | MT_RW | MT_SECURE), 47 {0} 48 }; 49 50 /******************************************************************************* 51 * Set up the pagetables as per the platform memory map & initialize the MMU 52 ******************************************************************************/ 53 const mmap_region_t *plat_get_mmio_map(void) 54 { 55 /* MMIO space */ 56 return tegra_mmap; 57 } 58 59 /******************************************************************************* 60 * Handler to get the System Counter Frequency 61 ******************************************************************************/ 62 unsigned int plat_get_syscnt_freq2(void) 63 { 64 return 19200000; 65 } 66 67 /******************************************************************************* 68 * Maximum supported UART controllers 69 ******************************************************************************/ 70 #define TEGRA210_MAX_UART_PORTS 5 71 72 /******************************************************************************* 73 * This variable holds the UART port base addresses 74 ******************************************************************************/ 75 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 76 0, /* undefined - treated as an error case */ 77 TEGRA_UARTA_BASE, 78 TEGRA_UARTB_BASE, 79 TEGRA_UARTC_BASE, 80 TEGRA_UARTD_BASE, 81 TEGRA_UARTE_BASE, 82 }; 83 84 /******************************************************************************* 85 * Retrieve the UART controller base to be used as the console 86 ******************************************************************************/ 87 uint32_t plat_get_console_from_id(int id) 88 { 89 if (id > TEGRA210_MAX_UART_PORTS) 90 return 0; 91 92 return tegra210_uart_addresses[id]; 93 } 94 95 /******************************************************************************* 96 * Initialize the GIC and SGIs 97 ******************************************************************************/ 98 void plat_gic_setup(void) 99 { 100 tegra_gic_setup(NULL, 0); 101 } 102