1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <desc_image_load.h> 14 #include <generic_delay_timer.h> 15 #ifdef SPD_opteed 16 #include <optee_utils.h> 17 #endif 18 #include <plat_arm.h> 19 #include <platform.h> 20 #include <platform_def.h> 21 #include <string.h> 22 #include <utils.h> 23 24 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 26 27 /* 28 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 29 * for `meminfo_t` data structure and fw_configs passed from BL1. 30 */ 31 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 32 33 /* Weak definitions may be overridden in specific ARM standard platform */ 34 #pragma weak bl2_early_platform_setup2 35 #pragma weak bl2_platform_setup 36 #pragma weak bl2_plat_arch_setup 37 #pragma weak bl2_plat_sec_mem_layout 38 39 #if LOAD_IMAGE_V2 40 41 #pragma weak bl2_plat_handle_post_image_load 42 43 #else /* LOAD_IMAGE_V2 */ 44 45 /******************************************************************************* 46 * This structure represents the superset of information that is passed to 47 * BL31, e.g. while passing control to it from BL2, bl31_params 48 * and other platform specific params 49 ******************************************************************************/ 50 typedef struct bl2_to_bl31_params_mem { 51 bl31_params_t bl31_params; 52 image_info_t bl31_image_info; 53 image_info_t bl32_image_info; 54 image_info_t bl33_image_info; 55 entry_point_info_t bl33_ep_info; 56 entry_point_info_t bl32_ep_info; 57 entry_point_info_t bl31_ep_info; 58 } bl2_to_bl31_params_mem_t; 59 60 61 static bl2_to_bl31_params_mem_t bl31_params_mem; 62 63 64 /* Weak definitions may be overridden in specific ARM standard platform */ 65 #pragma weak bl2_plat_get_bl31_params 66 #pragma weak bl2_plat_get_bl31_ep_info 67 #pragma weak bl2_plat_flush_bl31_params 68 #pragma weak bl2_plat_set_bl31_ep_info 69 #pragma weak bl2_plat_get_scp_bl2_meminfo 70 #pragma weak bl2_plat_get_bl32_meminfo 71 #pragma weak bl2_plat_set_bl32_ep_info 72 #pragma weak bl2_plat_get_bl33_meminfo 73 #pragma weak bl2_plat_set_bl33_ep_info 74 75 #if ARM_BL31_IN_DRAM 76 meminfo_t *bl2_plat_sec_mem_layout(void) 77 { 78 static meminfo_t bl2_dram_layout 79 __aligned(CACHE_WRITEBACK_GRANULE) = { 80 .total_base = BL31_BASE, 81 .total_size = (ARM_AP_TZC_DRAM1_BASE + 82 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, 83 .free_base = BL31_BASE, 84 .free_size = (ARM_AP_TZC_DRAM1_BASE + 85 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE 86 }; 87 88 return &bl2_dram_layout; 89 } 90 #else 91 meminfo_t *bl2_plat_sec_mem_layout(void) 92 { 93 return &bl2_tzram_layout; 94 } 95 #endif /* ARM_BL31_IN_DRAM */ 96 97 /******************************************************************************* 98 * This function assigns a pointer to the memory that the platform has kept 99 * aside to pass platform specific and trusted firmware related information 100 * to BL31. This memory is allocated by allocating memory to 101 * bl2_to_bl31_params_mem_t structure which is a superset of all the 102 * structure whose information is passed to BL31 103 * NOTE: This function should be called only once and should be done 104 * before generating params to BL31 105 ******************************************************************************/ 106 bl31_params_t *bl2_plat_get_bl31_params(void) 107 { 108 bl31_params_t *bl2_to_bl31_params; 109 110 /* 111 * Initialise the memory for all the arguments that needs to 112 * be passed to BL31 113 */ 114 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); 115 116 /* Assign memory for TF related information */ 117 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 118 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 119 120 /* Fill BL31 related information */ 121 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 122 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 123 VERSION_1, 0); 124 125 /* Fill BL32 related information if it exists */ 126 #ifdef BL32_BASE 127 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 128 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 129 VERSION_1, 0); 130 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 131 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 132 VERSION_1, 0); 133 #endif /* BL32_BASE */ 134 135 /* Fill BL33 related information */ 136 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 137 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 138 PARAM_EP, VERSION_1, 0); 139 140 /* BL33 expects to receive the primary CPU MPID (through x0) */ 141 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 142 143 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 144 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 145 VERSION_1, 0); 146 147 return bl2_to_bl31_params; 148 } 149 150 /* Flush the TF params and the TF plat params */ 151 void bl2_plat_flush_bl31_params(void) 152 { 153 flush_dcache_range((unsigned long)&bl31_params_mem, 154 sizeof(bl2_to_bl31_params_mem_t)); 155 } 156 157 /******************************************************************************* 158 * This function returns a pointer to the shared memory that the platform 159 * has kept to point to entry point information of BL31 to BL2 160 ******************************************************************************/ 161 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 162 { 163 #if DEBUG 164 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; 165 #endif 166 167 return &bl31_params_mem.bl31_ep_info; 168 } 169 #endif /* LOAD_IMAGE_V2 */ 170 171 /******************************************************************************* 172 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 173 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 174 * Copy it to a safe location before its reclaimed by later BL2 functionality. 175 ******************************************************************************/ 176 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout) 177 { 178 /* Initialize the console to provide early debug support */ 179 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 180 ARM_CONSOLE_BAUDRATE); 181 182 /* Setup the BL2 memory layout */ 183 bl2_tzram_layout = *mem_layout; 184 185 /* Initialise the IO layer and register platform IO devices */ 186 plat_arm_io_setup(); 187 188 #if LOAD_IMAGE_V2 189 if (tb_fw_config != 0U) 190 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 191 #endif 192 } 193 194 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 195 { 196 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 197 198 generic_delay_timer_init(); 199 } 200 201 /* 202 * Perform BL2 preload setup. Currently we initialise the dynamic 203 * configuration here. 204 */ 205 void bl2_plat_preload_setup(void) 206 { 207 #if LOAD_IMAGE_V2 208 arm_bl2_dyn_cfg_init(); 209 #endif 210 } 211 212 /* 213 * Perform ARM standard platform setup. 214 */ 215 void arm_bl2_platform_setup(void) 216 { 217 /* Initialize the secure environment */ 218 plat_arm_security_setup(); 219 220 #if defined(PLAT_ARM_MEM_PROT_ADDR) 221 arm_nor_psci_do_static_mem_protect(); 222 #endif 223 } 224 225 void bl2_platform_setup(void) 226 { 227 arm_bl2_platform_setup(); 228 } 229 230 /******************************************************************************* 231 * Perform the very early platform specific architectural setup here. At the 232 * moment this is only initializes the mmu in a quick and dirty way. 233 ******************************************************************************/ 234 void arm_bl2_plat_arch_setup(void) 235 { 236 arm_setup_page_tables(bl2_tzram_layout.total_base, 237 bl2_tzram_layout.total_size, 238 BL_CODE_BASE, 239 BL_CODE_END, 240 BL_RO_DATA_BASE, 241 BL_RO_DATA_END 242 #if USE_COHERENT_MEM 243 , BL_COHERENT_RAM_BASE, 244 BL_COHERENT_RAM_END 245 #endif 246 ); 247 248 #ifdef AARCH32 249 enable_mmu_secure(0); 250 #else 251 enable_mmu_el1(0); 252 #endif 253 } 254 255 void bl2_plat_arch_setup(void) 256 { 257 arm_bl2_plat_arch_setup(); 258 } 259 260 #if LOAD_IMAGE_V2 261 int arm_bl2_handle_post_image_load(unsigned int image_id) 262 { 263 int err = 0; 264 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 265 #ifdef SPD_opteed 266 bl_mem_params_node_t *pager_mem_params = NULL; 267 bl_mem_params_node_t *paged_mem_params = NULL; 268 #endif 269 assert(bl_mem_params); 270 271 switch (image_id) { 272 #ifdef AARCH64 273 case BL32_IMAGE_ID: 274 #ifdef SPD_opteed 275 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 276 assert(pager_mem_params); 277 278 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 279 assert(paged_mem_params); 280 281 err = parse_optee_header(&bl_mem_params->ep_info, 282 &pager_mem_params->image_info, 283 &paged_mem_params->image_info); 284 if (err != 0) { 285 WARN("OPTEE header parse error.\n"); 286 } 287 #endif 288 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 289 break; 290 #endif 291 292 case BL33_IMAGE_ID: 293 /* BL33 expects to receive the primary CPU MPID (through r0) */ 294 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 295 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 296 break; 297 298 #ifdef SCP_BL2_BASE 299 case SCP_BL2_IMAGE_ID: 300 /* The subsequent handling of SCP_BL2 is platform specific */ 301 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 302 if (err) { 303 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 304 } 305 break; 306 #endif 307 default: 308 /* Do nothing in default case */ 309 break; 310 } 311 312 return err; 313 } 314 315 /******************************************************************************* 316 * This function can be used by the platforms to update/use image 317 * information for given `image_id`. 318 ******************************************************************************/ 319 int bl2_plat_handle_post_image_load(unsigned int image_id) 320 { 321 return arm_bl2_handle_post_image_load(image_id); 322 } 323 324 #else /* LOAD_IMAGE_V2 */ 325 326 /******************************************************************************* 327 * Populate the extents of memory available for loading SCP_BL2 (if used), 328 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. 329 ******************************************************************************/ 330 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 331 { 332 *scp_bl2_meminfo = bl2_tzram_layout; 333 } 334 335 /******************************************************************************* 336 * Before calling this function BL31 is loaded in memory and its entrypoint 337 * is set by load_image. This is a placeholder for the platform to change 338 * the entrypoint of BL31 and set SPSR and security state. 339 * On ARM standard platforms we only set the security state of the entrypoint 340 ******************************************************************************/ 341 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, 342 entry_point_info_t *bl31_ep_info) 343 { 344 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 345 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 346 DISABLE_ALL_EXCEPTIONS); 347 } 348 349 350 /******************************************************************************* 351 * Before calling this function BL32 is loaded in memory and its entrypoint 352 * is set by load_image. This is a placeholder for the platform to change 353 * the entrypoint of BL32 and set SPSR and security state. 354 * On ARM standard platforms we only set the security state of the entrypoint 355 ******************************************************************************/ 356 #ifdef BL32_BASE 357 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 358 entry_point_info_t *bl32_ep_info) 359 { 360 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 361 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); 362 } 363 364 /******************************************************************************* 365 * Populate the extents of memory available for loading BL32 366 ******************************************************************************/ 367 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 368 { 369 /* 370 * Populate the extents of memory available for loading BL32. 371 */ 372 bl32_meminfo->total_base = BL32_BASE; 373 bl32_meminfo->free_base = BL32_BASE; 374 bl32_meminfo->total_size = 375 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 376 bl32_meminfo->free_size = 377 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 378 } 379 #endif /* BL32_BASE */ 380 381 /******************************************************************************* 382 * Before calling this function BL33 is loaded in memory and its entrypoint 383 * is set by load_image. This is a placeholder for the platform to change 384 * the entrypoint of BL33 and set SPSR and security state. 385 * On ARM standard platforms we only set the security state of the entrypoint 386 ******************************************************************************/ 387 void bl2_plat_set_bl33_ep_info(image_info_t *image, 388 entry_point_info_t *bl33_ep_info) 389 { 390 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 391 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); 392 } 393 394 /******************************************************************************* 395 * Populate the extents of memory available for loading BL33 396 ******************************************************************************/ 397 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 398 { 399 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; 400 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; 401 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; 402 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; 403 } 404 405 #endif /* LOAD_IMAGE_V2 */ 406