1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 18 #error ARMv7 target does not support LPAE MMU descriptors 19 #endif 20 21 /* 22 * Returns 1 if the provided granule size is supported, 0 otherwise. 23 */ 24 int xlat_arch_is_granule_size_supported(size_t size) 25 { 26 /* 27 * The Trusted Firmware uses long descriptor translation table format, 28 * which supports 4 KiB pages only. 29 */ 30 return (size == (4U * 1024U)); 31 } 32 33 size_t xlat_arch_get_max_supported_granule_size(void) 34 { 35 return 4U * 1024U; 36 } 37 38 #if ENABLE_ASSERTIONS 39 unsigned long long xlat_arch_get_max_supported_pa(void) 40 { 41 /* Physical address space size for long descriptor format. */ 42 return (1ULL << 40) - 1ULL; 43 } 44 #endif /* ENABLE_ASSERTIONS*/ 45 46 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused) 47 { 48 return (read_sctlr() & SCTLR_M_BIT) != 0; 49 } 50 51 void xlat_arch_tlbi_va(uintptr_t va) 52 { 53 /* 54 * Ensure the translation table write has drained into memory before 55 * invalidating the TLB entry. 56 */ 57 dsbishst(); 58 59 tlbimvaais(TLBI_ADDR(va)); 60 } 61 62 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime __unused) 63 { 64 /* 65 * Ensure the translation table write has drained into memory before 66 * invalidating the TLB entry. 67 */ 68 dsbishst(); 69 70 tlbimvaais(TLBI_ADDR(va)); 71 } 72 73 void xlat_arch_tlbi_va_sync(void) 74 { 75 /* Invalidate all entries from branch predictors. */ 76 bpiallis(); 77 78 /* 79 * A TLB maintenance instruction can complete at any time after 80 * it is issued, but is only guaranteed to be complete after the 81 * execution of DSB by the PE that executed the TLB maintenance 82 * instruction. After the TLB invalidate instruction is 83 * complete, no new memory accesses using the invalidated TLB 84 * entries will be observed by any observer of the system 85 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 86 * "Ordering and completion of TLB maintenance instructions". 87 */ 88 dsbish(); 89 90 /* 91 * The effects of a completed TLB maintenance instruction are 92 * only guaranteed to be visible on the PE that executed the 93 * instruction after the execution of an ISB instruction by the 94 * PE that executed the TLB maintenance instruction. 95 */ 96 isb(); 97 } 98 99 int xlat_arch_current_el(void) 100 { 101 /* 102 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 103 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 104 */ 105 return 3; 106 } 107 108 /******************************************************************************* 109 * Function for enabling the MMU in Secure PL1, assuming that the page tables 110 * have already been created. 111 ******************************************************************************/ 112 void enable_mmu_arch(unsigned int flags, 113 uint64_t *base_table, 114 unsigned long long max_pa, 115 uintptr_t max_va) 116 { 117 u_register_t mair0, ttbcr, sctlr; 118 uint64_t ttbr0; 119 120 assert(IS_IN_SECURE()); 121 122 sctlr = read_sctlr(); 123 assert((sctlr & SCTLR_M_BIT) == 0); 124 125 /* Invalidate TLBs at the current exception level */ 126 tlbiall(); 127 128 /* Set attributes in the right indices of the MAIR */ 129 mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 130 mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 131 ATTR_IWBWA_OWBWA_NTR_INDEX); 132 mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 133 ATTR_NON_CACHEABLE_INDEX); 134 135 /* 136 * Configure the control register for stage 1 of the PL1&0 translation 137 * regime. 138 */ 139 140 /* Use the Long-descriptor translation table format. */ 141 ttbcr = TTBCR_EAE_BIT; 142 143 /* 144 * Disable translation table walk for addresses that are translated 145 * using TTBR1. Therefore, only TTBR0 is used. 146 */ 147 ttbcr |= TTBCR_EPD1_BIT; 148 149 /* 150 * Limit the input address ranges and memory region sizes translated 151 * using TTBR0 to the given virtual address space size, if smaller than 152 * 32 bits. 153 */ 154 if (max_va != UINT32_MAX) { 155 uintptr_t virtual_addr_space_size = max_va + 1; 156 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 157 /* 158 * __builtin_ctzll(0) is undefined but here we are guaranteed 159 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 160 */ 161 ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size); 162 } 163 164 /* 165 * Set the cacheability and shareability attributes for memory 166 * associated with translation table walks using TTBR0. 167 */ 168 if (flags & XLAT_TABLE_NC) { 169 /* Inner & outer non-cacheable non-shareable. */ 170 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 171 TTBCR_RGN0_INNER_NC; 172 } else { 173 /* Inner & outer WBWA & shareable. */ 174 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 175 TTBCR_RGN0_INNER_WBA; 176 } 177 178 /* Set TTBR0 bits as well */ 179 ttbr0 = (uint64_t)(uintptr_t) base_table; 180 #if ARM_ARCH_AT_LEAST(8, 2) 181 /* 182 * Enable CnP bit so as to share page tables with all PEs. 183 * Mandatory for ARMv8.2 implementations. 184 */ 185 ttbr0 |= TTBR_CNP_BIT; 186 #endif 187 188 /* Now program the relevant system registers */ 189 write_mair0(mair0); 190 write_ttbcr(ttbcr); 191 write64_ttbr0(ttbr0); 192 write64_ttbr1(0); 193 194 /* 195 * Ensure all translation table writes have drained 196 * into memory, the TLB invalidation is complete, 197 * and translation register writes are committed 198 * before enabling the MMU 199 */ 200 dsbish(); 201 isb(); 202 203 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; 204 205 if (flags & DISABLE_DCACHE) 206 sctlr &= ~SCTLR_C_BIT; 207 else 208 sctlr |= SCTLR_C_BIT; 209 210 write_sctlr(sctlr); 211 212 /* Ensure the MMU enable takes effect immediately */ 213 isb(); 214 } 215