1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __MCUCFG_H__ 7 #define __MCUCFG_H__ 8 9 #include <mt8173_def.h> 10 #include <stdint.h> 11 12 struct mt8173_mcucfg_regs { 13 uint32_t mp0_ca7l_cache_config; 14 struct { 15 uint32_t mem_delsel0; 16 uint32_t mem_delsel1; 17 } mp0_cpu[4]; 18 uint32_t mp0_cache_mem_delsel0; 19 uint32_t mp0_cache_mem_delsel1; 20 uint32_t mp0_axi_config; 21 uint32_t mp0_misc_config[2]; 22 struct { 23 uint32_t rv_addr_lw; 24 uint32_t rv_addr_hw; 25 } mp0_rv_addr[4]; 26 uint32_t mp0_ca7l_cfg_dis; 27 uint32_t mp0_ca7l_clken_ctrl; 28 uint32_t mp0_ca7l_rst_ctrl; 29 uint32_t mp0_ca7l_misc_config; 30 uint32_t mp0_ca7l_dbg_pwr_ctrl; 31 uint32_t mp0_rw_rsvd0; 32 uint32_t mp0_rw_rsvd1; 33 uint32_t mp0_ro_rsvd; 34 uint32_t reserved0_0[100]; 35 uint32_t mp1_cpucfg; 36 uint32_t mp1_miscdbg; 37 uint32_t reserved0_1[13]; 38 uint32_t mp1_rst_ctl; 39 uint32_t mp1_clkenm_div; 40 uint32_t reserved0_2[7]; 41 uint32_t mp1_config_res; 42 uint32_t reserved0_3[13]; 43 struct { 44 uint32_t rv_addr_lw; 45 uint32_t rv_addr_hw; 46 } mp1_rv_addr[2]; 47 uint32_t reserved0_4[84]; 48 uint32_t mp0_rst_status; /* 0x400 */ 49 uint32_t mp0_dbg_ctrl; 50 uint32_t mp0_dbg_flag; 51 uint32_t mp0_ca7l_ir_mon; 52 struct { 53 uint32_t pc_lw; 54 uint32_t pc_hw; 55 uint32_t fp_arch32; 56 uint32_t sp_arch32; 57 uint32_t fp_arch64_lw; 58 uint32_t fp_arch64_hw; 59 uint32_t sp_arch64_lw; 60 uint32_t sp_arch64_hw; 61 } mp0_dbg_core[4]; 62 uint32_t dfd_ctrl; 63 uint32_t dfd_cnt_l; 64 uint32_t dfd_cnt_h; 65 uint32_t misccfg_mp0_rw_rsvd; 66 uint32_t misccfg_sec_vio_status0; 67 uint32_t misccfg_sec_vio_status1; 68 uint32_t reserved1[22]; 69 uint32_t misccfg_rw_rsvd; /* 0x500 */ 70 uint32_t mcusys_dbg_mon_sel_a; 71 uint32_t mcusys_dbg_mon; 72 uint32_t reserved2[61]; 73 uint32_t mcusys_config_a; /* 0x600 */ 74 uint32_t mcusys_config1_a; 75 uint32_t mcusys_gic_peribase_a; 76 uint32_t reserved3; 77 uint32_t sec_range0_start; /* 0x610 */ 78 uint32_t sec_range0_end; 79 uint32_t sec_range_enable; 80 uint32_t reserved4; 81 uint32_t int_pol_ctl[8]; /* 0x620 */ 82 uint32_t aclken_div; /* 0x640 */ 83 uint32_t pclken_div; 84 uint32_t l2c_sram_ctrl; 85 uint32_t armpll_jit_ctrl; 86 uint32_t cci_addrmap; /* 0x650 */ 87 uint32_t cci_config; 88 uint32_t cci_periphbase; 89 uint32_t cci_nevntcntovfl; 90 uint32_t cci_clk_ctrl; /* 0x660 */ 91 uint32_t cci_acel_s1_ctrl; 92 uint32_t bus_fabric_dcm_ctrl; 93 uint32_t reserved5; 94 uint32_t xgpt_ctl; /* 0x670 */ 95 uint32_t xgpt_idx; 96 uint32_t ptpod2_ctl0; 97 uint32_t ptpod2_ctl1; 98 uint32_t mcusys_revid; 99 uint32_t mcusys_rw_rsvd0; 100 uint32_t mcusys_rw_rsvd1; 101 }; 102 103 static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; 104 105 /* cpu boot mode */ 106 #define MP0_CPUCFG_64BIT_SHIFT 12 107 #define MP1_CPUCFG_64BIT_SHIFT 28 108 #define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) 109 #define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) 110 111 /* scu related */ 112 enum { 113 MP0_ACINACTM_SHIFT = 4, 114 MP1_ACINACTM_SHIFT = 0, 115 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, 116 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT 117 }; 118 119 enum { 120 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, 121 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, 122 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, 123 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, 124 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, 125 126 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 127 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 128 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 129 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 130 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 131 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 132 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 133 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 134 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 135 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 136 }; 137 138 enum { 139 MP1_AINACTS_SHIFT = 4, 140 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT 141 }; 142 143 enum { 144 MP1_SW_CG_GEN_SHIFT = 12, 145 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT 146 }; 147 148 enum { 149 MP1_L2RSTDISABLE_SHIFT = 14, 150 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT 151 }; 152 153 /* cci clock control related */ 154 enum { 155 MCU_BUS_DCM_EN = 1 << 8 156 }; 157 158 /* l2c sram control related */ 159 enum { 160 L2C_SRAM_DCM_EN = 1 << 0 161 }; 162 163 /* bus fabric dcm control related */ 164 enum { 165 PSYS_ADB400_DCM_EN = 1 << 29, 166 GPU_ADB400_DCM_EN = 1 << 28, 167 168 EMI1_ADB400_DCM_EN = 1 << 27, 169 EMI_ADB400_DCM_EN = 1 << 26, 170 INFRA_ADB400_DCM_EN = 1 << 25, 171 L2C_ADB400_DCM_EN = 1 << 24, 172 173 MP0_ADB400_DCM_EN = 1 << 23, 174 CCI400_CK_ONLY_DCM_EN = 1 << 22, 175 L2C_IDLE_DCM_EN = 1 << 21, 176 177 CA15U_ADB_DYNAMIC_CG_EN = 1 << 19, 178 CA7L_ADB_DYNAMIC_CG_EN = 1 << 18, 179 L2C_ADB_DYNAMIC_CG_EN = 1 << 17, 180 181 EMICLK_EMI1_DYNAMIC_CG_EN = 1 << 12, 182 183 INFRACLK_PSYS_DYNAMIC_CG_EN = 1 << 11, 184 EMICLK_GPU_DYNAMIC_CG_EN = 1 << 10, 185 EMICLK_EMI_DYNAMIC_CG_EN = 1 << 8, 186 187 CCI400_SLV_RW_DCM_EN = 1 << 7, 188 CCI400_SLV_DCM_EN = 1 << 5, 189 190 ACLK_PSYS_DYNAMIC_CG_EN = 1 << 3, 191 ACLK_GPU_DYNAMIC_CG_EN = 1 << 2, 192 ACLK_EMI_DYNAMIC_CG_EN = 1 << 1, 193 ACLK_INFRA_DYNAMIC_CG_EN = 1 << 0, 194 195 /* adb400 related */ 196 ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN | 197 EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN | 198 INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN | 199 MP0_ADB400_DCM_EN, 200 201 /* cci400 related */ 202 CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN | 203 CCI400_SLV_DCM_EN, 204 205 /* adb clock related */ 206 ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN | 207 L2C_ADB_DYNAMIC_CG_EN, 208 209 /* emi clock related */ 210 EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN | 211 EMICLK_GPU_DYNAMIC_CG_EN | 212 EMICLK_EMI_DYNAMIC_CG_EN, 213 214 /* bus clock related */ 215 ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN | 216 ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN, 217 }; 218 219 #endif /* __MCUCFG_H__ */ 220