1# 2# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 8 drivers/arm/gic/v2/gicv2_main.c \ 9 drivers/arm/gic/v2/gicv2_helpers.c \ 10 plat/common/plat_gicv2.c \ 11 plat/arm/common/arm_gicv2.c 12 13JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 14 plat/arm/common/arm_cci.c 15 16JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 17 plat/arm/board/juno/juno_security.c \ 18 plat/arm/board/juno/juno_trng.c \ 19 plat/arm/common/arm_tzc400.c 20 21ifneq (${ENABLE_STACK_PROTECTOR}, 0) 22JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 23endif 24 25PLAT_INCLUDES := -Iplat/arm/board/juno/include 26 27PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S 28 29# Flag to enable support for AArch32 state on JUNO 30JUNO_AARCH32_EL3_RUNTIME := 0 31$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 32$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 33 34# Flag to enable support for TZMP1 on JUNO 35JUNO_TZMP1 := 0 36$(eval $(call assert_boolean,JUNO_TZMP1)) 37ifeq (${JUNO_TZMP1}, 1) 38$(eval $(call add_define,JUNO_TZMP1)) 39endif 40 41ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 42# Include BL32 in FIP 43NEED_BL32 := yes 44# BL31 is not required 45override BL31_SOURCES = 46 47# The BL32 needs to be built separately invoking the AARCH32 compiler and 48# be specifed via `BL32` build option. 49 ifneq (${ARCH}, aarch32) 50 override BL32_SOURCES = 51 endif 52endif 53 54ifeq (${ARCH},aarch64) 55BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 56 lib/cpus/aarch64/cortex_a57.S \ 57 lib/cpus/aarch64/cortex_a72.S \ 58 plat/arm/board/juno/juno_bl1_setup.c \ 59 ${JUNO_INTERCONNECT_SOURCES} \ 60 ${JUNO_SECURITY_SOURCES} 61 62BL2_SOURCES += lib/utils/mem_region.c \ 63 plat/arm/board/juno/juno_bl2_setup.c \ 64 plat/arm/common/arm_nor_psci_mem_protect.c \ 65 ${JUNO_SECURITY_SOURCES} 66 67BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 68 69BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 70 lib/cpus/aarch64/cortex_a57.S \ 71 lib/cpus/aarch64/cortex_a72.S \ 72 lib/utils/mem_region.c \ 73 plat/arm/board/juno/juno_topology.c \ 74 plat/arm/board/common/drivers/norflash/norflash.c \ 75 plat/arm/common/arm_nor_psci_mem_protect.c \ 76 ${JUNO_GIC_SOURCES} \ 77 ${JUNO_INTERCONNECT_SOURCES} \ 78 ${JUNO_SECURITY_SOURCES} 79endif 80 81# Errata workarounds for Cortex-A53: 82ERRATA_A53_826319 := 1 83ERRATA_A53_835769 := 1 84ERRATA_A53_836870 := 1 85ERRATA_A53_843419 := 1 86ERRATA_A53_855873 := 1 87 88# Errata workarounds for Cortex-A57: 89ERRATA_A57_806969 := 0 90ERRATA_A57_813419 := 1 91ERRATA_A57_813420 := 1 92ERRATA_A57_826974 := 1 93ERRATA_A57_826977 := 1 94ERRATA_A57_828024 := 1 95ERRATA_A57_829520 := 1 96ERRATA_A57_833471 := 1 97ERRATA_A57_859972 := 0 98 99# Errata workarounds for Cortex-A72: 100ERRATA_A72_859971 := 0 101 102# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 103# power down sequence 104SKIP_A57_L1_FLUSH_PWR_DWN := 1 105 106# Disable the PSCI platform compatibility layer 107ENABLE_PLAT_COMPAT := 0 108 109# Enable memory map related constants optimisation 110ARM_BOARD_OPTIMISE_MEM := 1 111 112# Do not enable SVE 113ENABLE_SVE_FOR_NS := 0 114 115# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 116# SCP during power management operations and for SCP RAM Firmware transfer. 117CSS_USE_SCMI_SDS_DRIVER := 1 118 119include plat/arm/board/common/board_css.mk 120include plat/arm/common/arm_common.mk 121include plat/arm/soc/common/soc_css.mk 122include plat/arm/css/common/css_common.mk 123 124