1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8#include <xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 16} 17 18 19SECTIONS 20{ 21 . = BL2_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL2_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl2_entrypoint.o(.text*) 29 *(.text*) 30 *(.vectors) 31 . = NEXT(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >RAM 34 35 .rodata . : { 36 __RODATA_START__ = .; 37 *(.rodata*) 38 39 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 40 . = ALIGN(8); 41 __PARSER_LIB_DESCS_START__ = .; 42 KEEP(*(.img_parser_lib_descs)) 43 __PARSER_LIB_DESCS_END__ = .; 44 45 . = NEXT(PAGE_SIZE); 46 __RODATA_END__ = .; 47 } >RAM 48#else 49 ro . : { 50 __RO_START__ = .; 51 *bl2_entrypoint.o(.text*) 52 *(.text*) 53 *(.rodata*) 54 55 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 56 . = ALIGN(8); 57 __PARSER_LIB_DESCS_START__ = .; 58 KEEP(*(.img_parser_lib_descs)) 59 __PARSER_LIB_DESCS_END__ = .; 60 61 *(.vectors) 62 __RO_END_UNALIGNED__ = .; 63 /* 64 * Memory page(s) mapped to this section will be marked as 65 * read-only, executable. No RW data from the next section must 66 * creep in. Ensure the rest of the current memory page is unused. 67 */ 68 . = NEXT(PAGE_SIZE); 69 __RO_END__ = .; 70 } >RAM 71#endif 72 73 /* 74 * Define a linker symbol to mark start of the RW memory area for this 75 * image. 76 */ 77 __RW_START__ = . ; 78 79 /* 80 * .data must be placed at a lower address than the stacks if the stack 81 * protector is enabled. Alternatively, the .data.stack_protector_canary 82 * section can be placed independently of the main .data section. 83 */ 84 .data . : { 85 __DATA_START__ = .; 86 *(.data*) 87 __DATA_END__ = .; 88 } >RAM 89 90 stacks (NOLOAD) : { 91 __STACKS_START__ = .; 92 *(tzfw_normal_stacks) 93 __STACKS_END__ = .; 94 } >RAM 95 96 /* 97 * The .bss section gets initialised to 0 at runtime. 98 * Its base address should be 16-byte aligned for better performance of the 99 * zero-initialization code. 100 */ 101 .bss : ALIGN(16) { 102 __BSS_START__ = .; 103 *(SORT_BY_ALIGNMENT(.bss*)) 104 *(COMMON) 105 __BSS_END__ = .; 106 } >RAM 107 108 /* 109 * The xlat_table section is for full, aligned page tables (4K). 110 * Removing them from .bss avoids forcing 4K alignment on 111 * the .bss section. The tables are initialized to zero by the translation 112 * tables library. 113 */ 114 xlat_table (NOLOAD) : { 115 *(xlat_table) 116 } >RAM 117 118#if USE_COHERENT_MEM 119 /* 120 * The base address of the coherent memory section must be page-aligned (4K) 121 * to guarantee that the coherent data are stored on their own pages and 122 * are not mixed with normal data. This is required to set up the correct 123 * memory attributes for the coherent data page tables. 124 */ 125 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 126 __COHERENT_RAM_START__ = .; 127 *(tzfw_coherent_mem) 128 __COHERENT_RAM_END_UNALIGNED__ = .; 129 /* 130 * Memory page(s) mapped to this section will be marked 131 * as device memory. No other unexpected data must creep in. 132 * Ensure the rest of the current memory page is unused. 133 */ 134 . = NEXT(PAGE_SIZE); 135 __COHERENT_RAM_END__ = .; 136 } >RAM 137#endif 138 139 /* 140 * Define a linker symbol to mark end of the RW memory area for this 141 * image. 142 */ 143 __RW_END__ = .; 144 __BL2_END__ = .; 145 146 __BSS_SIZE__ = SIZEOF(.bss); 147 148#if USE_COHERENT_MEM 149 __COHERENT_RAM_UNALIGNED_SIZE__ = 150 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 151#endif 152 153 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 154} 155