1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include <gicv2.h> 13 #include <interrupt_props.h> 14 #include <spinlock.h> 15 #include "../common/gic_common_private.h" 16 #include "gicv2_private.h" 17 18 static const gicv2_driver_data_t *driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 static spinlock_t gic_lock; 26 27 /******************************************************************************* 28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 29 * and set the priority mask register to allow all interrupts to trickle in. 30 ******************************************************************************/ 31 void gicv2_cpuif_enable(void) 32 { 33 unsigned int val; 34 35 assert(driver_data); 36 assert(driver_data->gicc_base); 37 38 /* 39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 40 * bypass. 41 */ 42 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 43 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 44 45 /* Program the idle priority in the PMR */ 46 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 47 gicc_write_ctlr(driver_data->gicc_base, val); 48 } 49 50 /******************************************************************************* 51 * Place the cpu interface in a state where it can never make a cpu exit wfi as 52 * as result of an asserted interrupt. This is critical for powering down a cpu 53 ******************************************************************************/ 54 void gicv2_cpuif_disable(void) 55 { 56 unsigned int val; 57 58 assert(driver_data); 59 assert(driver_data->gicc_base); 60 61 /* Disable secure, non-secure interrupts and disable their bypass */ 62 val = gicc_read_ctlr(driver_data->gicc_base); 63 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 64 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 65 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 66 gicc_write_ctlr(driver_data->gicc_base, val); 67 } 68 69 /******************************************************************************* 70 * Per cpu gic distributor setup which will be done by all cpus after a cold 71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 72 ******************************************************************************/ 73 void gicv2_pcpu_distif_init(void) 74 { 75 unsigned int ctlr; 76 77 assert(driver_data); 78 assert(driver_data->gicd_base); 79 80 #if !ERROR_DEPRECATED 81 if (driver_data->interrupt_props != NULL) { 82 #endif 83 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 84 driver_data->interrupt_props, 85 driver_data->interrupt_props_num); 86 #if !ERROR_DEPRECATED 87 } else { 88 /* 89 * Suppress deprecated declaration warnings in compatibility 90 * function 91 */ 92 #pragma GCC diagnostic push 93 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 94 assert(driver_data->g0_interrupt_array); 95 gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, 96 driver_data->g0_interrupt_num, 97 driver_data->g0_interrupt_array); 98 #pragma GCC diagnostic pop 99 } 100 #endif 101 102 /* Enable G0 interrupts if not already */ 103 ctlr = gicd_read_ctlr(driver_data->gicd_base); 104 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) { 105 gicd_write_ctlr(driver_data->gicd_base, 106 ctlr | CTLR_ENABLE_G0_BIT); 107 } 108 } 109 110 /******************************************************************************* 111 * Global gic distributor init which will be done by the primary cpu after a 112 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 113 * then enables the secure GIC distributor interface. 114 ******************************************************************************/ 115 void gicv2_distif_init(void) 116 { 117 unsigned int ctlr; 118 119 assert(driver_data); 120 assert(driver_data->gicd_base); 121 122 /* Disable the distributor before going further */ 123 ctlr = gicd_read_ctlr(driver_data->gicd_base); 124 gicd_write_ctlr(driver_data->gicd_base, 125 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 126 127 /* Set the default attribute of all SPIs */ 128 gicv2_spis_configure_defaults(driver_data->gicd_base); 129 130 #if !ERROR_DEPRECATED 131 if (driver_data->interrupt_props != NULL) { 132 #endif 133 gicv2_secure_spis_configure_props(driver_data->gicd_base, 134 driver_data->interrupt_props, 135 driver_data->interrupt_props_num); 136 #if !ERROR_DEPRECATED 137 } else { 138 /* 139 * Suppress deprecated declaration warnings in compatibility 140 * function 141 */ 142 #pragma GCC diagnostic push 143 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 144 145 assert(driver_data->g0_interrupt_array); 146 147 /* Configure the G0 SPIs */ 148 gicv2_secure_spis_configure(driver_data->gicd_base, 149 driver_data->g0_interrupt_num, 150 driver_data->g0_interrupt_array); 151 #pragma GCC diagnostic pop 152 } 153 #endif 154 155 /* Re-enable the secure SPIs now that they have been configured */ 156 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 157 } 158 159 /******************************************************************************* 160 * Initialize the ARM GICv2 driver with the provided platform inputs 161 ******************************************************************************/ 162 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 163 { 164 unsigned int gic_version; 165 assert(plat_driver_data); 166 assert(plat_driver_data->gicd_base); 167 assert(plat_driver_data->gicc_base); 168 169 #if !ERROR_DEPRECATED 170 if (plat_driver_data->interrupt_props == NULL) { 171 /* Interrupt properties array size must be 0 */ 172 assert(plat_driver_data->interrupt_props_num == 0); 173 174 /* 175 * Suppress deprecated declaration warnings in compatibility 176 * function 177 */ 178 #pragma GCC diagnostic push 179 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 180 181 /* 182 * If there are no interrupts of a particular type, then the 183 * number of interrupts of that type should be 0 and vice-versa. 184 */ 185 assert(plat_driver_data->g0_interrupt_array ? 186 plat_driver_data->g0_interrupt_num : 187 plat_driver_data->g0_interrupt_num == 0); 188 #pragma GCC diagnostic pop 189 190 WARN("Using deprecated integer interrupt array in " 191 "gicv2_driver_data_t\n"); 192 WARN("Please migrate to using an interrupt_prop_t array\n"); 193 } 194 #else 195 assert(plat_driver_data->interrupt_props_num > 0 ? 196 plat_driver_data->interrupt_props != NULL : 1); 197 #endif 198 199 /* Ensure that this is a GICv2 system */ 200 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 201 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 202 & PIDR2_ARCH_REV_MASK; 203 204 /* 205 * GICv1 with security extension complies with trusted firmware 206 * GICv2 driver as far as virtualization and few tricky power 207 * features are not used. GICv2 features that are not supported 208 * by GICv1 with Security Extensions are: 209 * - virtual interrupt support. 210 * - wake up events. 211 * - writeable GIC state register (for power sequences) 212 * - interrupt priority drop. 213 * - interrupt signal bypass. 214 */ 215 assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1); 216 217 driver_data = plat_driver_data; 218 219 /* 220 * The GIC driver data is initialized by the primary CPU with caches 221 * enabled. When the secondary CPU boots up, it initializes the 222 * GICC/GICR interface with the caches disabled. Hence flush the 223 * driver_data to ensure coherency. This is not required if the 224 * platform has HW_ASSISTED_COHERENCY enabled. 225 */ 226 #if !HW_ASSISTED_COHERENCY 227 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 228 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 229 #endif 230 INFO("ARM GICv2 driver initialized\n"); 231 } 232 233 /****************************************************************************** 234 * This function returns whether FIQ is enabled in the GIC CPU interface. 235 *****************************************************************************/ 236 unsigned int gicv2_is_fiq_enabled(void) 237 { 238 unsigned int gicc_ctlr; 239 240 assert(driver_data); 241 assert(driver_data->gicc_base); 242 243 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 244 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; 245 } 246 247 /******************************************************************************* 248 * This function returns the type of the highest priority pending interrupt at 249 * the GIC cpu interface. The return values can be one of the following : 250 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 251 * 0 - 1019 : The interrupt type is secure Group 0. 252 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 253 * sufficient priority to be signaled 254 ******************************************************************************/ 255 unsigned int gicv2_get_pending_interrupt_type(void) 256 { 257 assert(driver_data); 258 assert(driver_data->gicc_base); 259 260 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 261 } 262 263 /******************************************************************************* 264 * This function returns the id of the highest priority pending interrupt at 265 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 266 * interrupt pending. 267 ******************************************************************************/ 268 unsigned int gicv2_get_pending_interrupt_id(void) 269 { 270 unsigned int id; 271 272 assert(driver_data); 273 assert(driver_data->gicc_base); 274 275 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 276 277 /* 278 * Find out which non-secure interrupt it is under the assumption that 279 * the GICC_CTLR.AckCtl bit is 0. 280 */ 281 if (id == PENDING_G1_INTID) 282 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 283 284 return id; 285 } 286 287 /******************************************************************************* 288 * This functions reads the GIC cpu interface Interrupt Acknowledge register 289 * to start handling the pending secure 0 interrupt. It returns the 290 * contents of the IAR. 291 ******************************************************************************/ 292 unsigned int gicv2_acknowledge_interrupt(void) 293 { 294 assert(driver_data); 295 assert(driver_data->gicc_base); 296 297 return gicc_read_IAR(driver_data->gicc_base); 298 } 299 300 /******************************************************************************* 301 * This functions writes the GIC cpu interface End Of Interrupt register with 302 * the passed value to finish handling the active secure group 0 interrupt. 303 ******************************************************************************/ 304 void gicv2_end_of_interrupt(unsigned int id) 305 { 306 assert(driver_data); 307 assert(driver_data->gicc_base); 308 309 gicc_write_EOIR(driver_data->gicc_base, id); 310 } 311 312 /******************************************************************************* 313 * This function returns the type of the interrupt id depending upon the group 314 * this interrupt has been configured under by the interrupt controller i.e. 315 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 316 * one for Group 1 non secure interrupt. 317 ******************************************************************************/ 318 unsigned int gicv2_get_interrupt_group(unsigned int id) 319 { 320 assert(driver_data); 321 assert(driver_data->gicd_base); 322 323 return gicd_get_igroupr(driver_data->gicd_base, id); 324 } 325 326 /******************************************************************************* 327 * This function returns the priority of the interrupt the processor is 328 * currently servicing. 329 ******************************************************************************/ 330 unsigned int gicv2_get_running_priority(void) 331 { 332 assert(driver_data); 333 assert(driver_data->gicc_base); 334 335 return gicc_read_rpr(driver_data->gicc_base); 336 } 337 338 /******************************************************************************* 339 * This function sets the GICv2 target mask pattern for the current PE. The PE 340 * target mask is used to translate linear PE index (returned by platform core 341 * position) to a bit mask used when targeting interrupts to a PE, viz. when 342 * raising SGIs and routing SPIs. 343 ******************************************************************************/ 344 void gicv2_set_pe_target_mask(unsigned int proc_num) 345 { 346 assert(driver_data); 347 assert(driver_data->gicd_base); 348 assert(driver_data->target_masks); 349 assert(proc_num < GICV2_MAX_TARGET_PE); 350 assert(proc_num < driver_data->target_masks_num); 351 352 /* Return if the target mask is already populated */ 353 if (driver_data->target_masks[proc_num]) 354 return; 355 356 /* 357 * Update target register corresponding to this CPU and flush for it to 358 * be visible to other CPUs. 359 */ 360 if (driver_data->target_masks[proc_num] == 0) { 361 driver_data->target_masks[proc_num] = 362 gicv2_get_cpuif_id(driver_data->gicd_base); 363 #if !HW_ASSISTED_COHERENCY 364 /* 365 * PEs only update their own masks. Primary updates it with 366 * caches on. But because secondaries does it with caches off, 367 * all updates go to memory directly, and there's no danger of 368 * secondaries overwriting each others' mask, despite 369 * target_masks[] not being cache line aligned. 370 */ 371 flush_dcache_range((uintptr_t) 372 &driver_data->target_masks[proc_num], 373 sizeof(driver_data->target_masks[proc_num])); 374 #endif 375 } 376 } 377 378 /******************************************************************************* 379 * This function returns the active status of the interrupt (either because the 380 * state is active, or active and pending). 381 ******************************************************************************/ 382 unsigned int gicv2_get_interrupt_active(unsigned int id) 383 { 384 assert(driver_data); 385 assert(driver_data->gicd_base); 386 assert(id <= MAX_SPI_ID); 387 388 return gicd_get_isactiver(driver_data->gicd_base, id); 389 } 390 391 /******************************************************************************* 392 * This function enables the interrupt identified by id. 393 ******************************************************************************/ 394 void gicv2_enable_interrupt(unsigned int id) 395 { 396 assert(driver_data); 397 assert(driver_data->gicd_base); 398 assert(id <= MAX_SPI_ID); 399 400 /* 401 * Ensure that any shared variable updates depending on out of band 402 * interrupt trigger are observed before enabling interrupt. 403 */ 404 dsbishst(); 405 gicd_set_isenabler(driver_data->gicd_base, id); 406 } 407 408 /******************************************************************************* 409 * This function disables the interrupt identified by id. 410 ******************************************************************************/ 411 void gicv2_disable_interrupt(unsigned int id) 412 { 413 assert(driver_data); 414 assert(driver_data->gicd_base); 415 assert(id <= MAX_SPI_ID); 416 417 /* 418 * Disable interrupt, and ensure that any shared variable updates 419 * depending on out of band interrupt trigger are observed afterwards. 420 */ 421 gicd_set_icenabler(driver_data->gicd_base, id); 422 dsbishst(); 423 } 424 425 /******************************************************************************* 426 * This function sets the interrupt priority as supplied for the given interrupt 427 * id. 428 ******************************************************************************/ 429 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 430 { 431 assert(driver_data); 432 assert(driver_data->gicd_base); 433 assert(id <= MAX_SPI_ID); 434 435 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 436 } 437 438 /******************************************************************************* 439 * This function assigns group for the interrupt identified by id. The group can 440 * be any of GICV2_INTR_GROUP* 441 ******************************************************************************/ 442 void gicv2_set_interrupt_type(unsigned int id, unsigned int type) 443 { 444 assert(driver_data); 445 assert(driver_data->gicd_base); 446 assert(id <= MAX_SPI_ID); 447 448 /* Serialize read-modify-write to Distributor registers */ 449 spin_lock(&gic_lock); 450 switch (type) { 451 case GICV2_INTR_GROUP1: 452 gicd_set_igroupr(driver_data->gicd_base, id); 453 break; 454 case GICV2_INTR_GROUP0: 455 gicd_clr_igroupr(driver_data->gicd_base, id); 456 break; 457 default: 458 assert(0); 459 break; 460 } 461 spin_unlock(&gic_lock); 462 } 463 464 /******************************************************************************* 465 * This function raises the specified SGI to requested targets. 466 * 467 * The proc_num parameter must be the linear index of the target PE in the 468 * system. 469 ******************************************************************************/ 470 void gicv2_raise_sgi(int sgi_num, int proc_num) 471 { 472 unsigned int sgir_val, target; 473 474 assert(driver_data); 475 assert(proc_num < GICV2_MAX_TARGET_PE); 476 assert(driver_data->gicd_base); 477 478 /* 479 * Target masks array must have been supplied, and the core position 480 * should be valid. 481 */ 482 assert(driver_data->target_masks); 483 assert(proc_num < driver_data->target_masks_num); 484 485 /* Don't raise SGI if the mask hasn't been populated */ 486 target = driver_data->target_masks[proc_num]; 487 assert(target != 0); 488 489 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); 490 491 /* 492 * Ensure that any shared variable updates depending on out of band 493 * interrupt trigger are observed before raising SGI. 494 */ 495 dsbishst(); 496 gicd_write_sgir(driver_data->gicd_base, sgir_val); 497 } 498 499 /******************************************************************************* 500 * This function sets the interrupt routing for the given SPI interrupt id. 501 * The interrupt routing is specified in routing mode. The proc_num parameter is 502 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 503 * all PEs. 504 ******************************************************************************/ 505 void gicv2_set_spi_routing(unsigned int id, int proc_num) 506 { 507 int target; 508 509 assert(driver_data); 510 assert(driver_data->gicd_base); 511 512 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 513 514 /* 515 * Target masks array must have been supplied, and the core position 516 * should be valid. 517 */ 518 assert(driver_data->target_masks); 519 assert(proc_num < GICV2_MAX_TARGET_PE); 520 assert(proc_num < driver_data->target_masks_num); 521 522 if (proc_num < 0) { 523 /* Target all PEs */ 524 target = GIC_TARGET_CPU_MASK; 525 } else { 526 /* Don't route interrupt if the mask hasn't been populated */ 527 target = driver_data->target_masks[proc_num]; 528 assert(target != 0); 529 } 530 531 gicd_set_itargetsr(driver_data->gicd_base, id, target); 532 } 533 534 /******************************************************************************* 535 * This function clears the pending status of an interrupt identified by id. 536 ******************************************************************************/ 537 void gicv2_clear_interrupt_pending(unsigned int id) 538 { 539 assert(driver_data); 540 assert(driver_data->gicd_base); 541 542 /* SGIs can't be cleared pending */ 543 assert(id >= MIN_PPI_ID); 544 545 /* 546 * Clear pending interrupt, and ensure that any shared variable updates 547 * depending on out of band interrupt trigger are observed afterwards. 548 */ 549 gicd_set_icpendr(driver_data->gicd_base, id); 550 dsbishst(); 551 } 552 553 /******************************************************************************* 554 * This function sets the pending status of an interrupt identified by id. 555 ******************************************************************************/ 556 void gicv2_set_interrupt_pending(unsigned int id) 557 { 558 assert(driver_data); 559 assert(driver_data->gicd_base); 560 561 /* SGIs can't be cleared pending */ 562 assert(id >= MIN_PPI_ID); 563 564 /* 565 * Ensure that any shared variable updates depending on out of band 566 * interrupt trigger are observed before setting interrupt pending. 567 */ 568 dsbishst(); 569 gicd_set_ispendr(driver_data->gicd_base, id); 570 } 571 572 /******************************************************************************* 573 * This function sets the PMR register with the supplied value. Returns the 574 * original PMR. 575 ******************************************************************************/ 576 unsigned int gicv2_set_pmr(unsigned int mask) 577 { 578 unsigned int old_mask; 579 580 assert(driver_data); 581 assert(driver_data->gicc_base); 582 583 old_mask = gicc_read_pmr(driver_data->gicc_base); 584 585 /* 586 * Order memory updates w.r.t. PMR write, and ensure they're visible 587 * before potential out of band interrupt trigger because of PMR update. 588 */ 589 dmbishst(); 590 gicc_write_pmr(driver_data->gicc_base, mask); 591 dsbishst(); 592 593 return old_mask; 594 } 595