1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __PLAT_ARM_H__ 7 #define __PLAT_ARM_H__ 8 9 #include <arm_xlat_tables.h> 10 #include <bakery_lock.h> 11 #include <cassert.h> 12 #include <cpu_data.h> 13 #include <stdint.h> 14 #include <tzc_common.h> 15 #include <utils_def.h> 16 17 /******************************************************************************* 18 * Forward declarations 19 ******************************************************************************/ 20 struct bl31_params; 21 struct meminfo; 22 struct image_info; 23 struct bl_params; 24 25 typedef struct arm_tzc_regions_info { 26 unsigned long long base; 27 unsigned long long end; 28 tzc_region_attributes_t sec_attr; 29 unsigned int nsaid_permissions; 30 } arm_tzc_regions_info_t; 31 32 /******************************************************************************* 33 * Default mapping definition of the TrustZone Controller for ARM standard 34 * platforms. 35 * Configure: 36 * - Region 0 with no access; 37 * - Region 1 with secure access only; 38 * - the remaining DRAM regions access from the given Non-Secure masters. 39 ******************************************************************************/ 40 #if ENABLE_SPM 41 #define ARM_TZC_REGIONS_DEF \ 42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 43 TZC_REGION_S_RDWR, 0}, \ 44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ 49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 50 PLAT_ARM_TZC_NS_DEV_ACCESS} 51 52 #else 53 #define ARM_TZC_REGIONS_DEF \ 54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 55 TZC_REGION_S_RDWR, 0}, \ 56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS} 60 #endif 61 62 #define ARM_CASSERT_MMAP \ 63 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 64 assert_plat_arm_mmap_mismatch); \ 65 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 66 <= MAX_MMAP_REGIONS, \ 67 assert_max_mmap_regions); 68 69 /* 70 * Utility functions common to ARM standard platforms 71 */ 72 void arm_setup_page_tables(uintptr_t total_base, 73 size_t total_size, 74 uintptr_t code_start, 75 uintptr_t code_limit, 76 uintptr_t rodata_start, 77 uintptr_t rodata_limit 78 #if USE_COHERENT_MEM 79 , uintptr_t coh_start, 80 uintptr_t coh_limit 81 #endif 82 ); 83 84 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) 85 /* 86 * Use this macro to instantiate lock before it is used in below 87 * arm_lock_xxx() macros 88 */ 89 #define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock) 90 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 91 /* 92 * These are wrapper macros to the Coherent Memory Bakery Lock API. 93 */ 94 #define arm_lock_init() bakery_lock_init(&arm_lock) 95 #define arm_lock_get() bakery_lock_get(&arm_lock) 96 #define arm_lock_release() bakery_lock_release(&arm_lock) 97 98 #else 99 100 /* 101 * Empty macros for all other BL stages other than BL31 and BL32 102 */ 103 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 104 #define ARM_LOCK_GET_INSTANCE 0 105 #define arm_lock_init() 106 #define arm_lock_get() 107 #define arm_lock_release() 108 109 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ 110 111 #if ARM_RECOM_STATE_ID_ENC 112 /* 113 * Macros used to parse state information from State-ID if it is using the 114 * recommended encoding for State-ID. 115 */ 116 #define ARM_LOCAL_PSTATE_WIDTH 4 117 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 118 119 /* Macros to construct the composite power state */ 120 121 /* Make composite power state parameter till power level 0 */ 122 #if PSCI_EXTENDED_STATE_ID 123 124 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 125 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 126 #else 127 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 128 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 129 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 130 ((type) << PSTATE_TYPE_SHIFT)) 131 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 132 133 /* Make composite power state parameter till power level 1 */ 134 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 135 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 136 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 137 138 /* Make composite power state parameter till power level 2 */ 139 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 140 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 141 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 142 143 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 144 145 /* ARM State switch error codes */ 146 #define STATE_SW_E_PARAM (-2) 147 #define STATE_SW_E_DENIED (-3) 148 149 /* IO storage utility functions */ 150 void arm_io_setup(void); 151 152 /* Security utility functions */ 153 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); 154 struct tzc_dmc500_driver_data; 155 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 156 const arm_tzc_regions_info_t *tzc_regions); 157 158 /* Systimer utility function */ 159 void arm_configure_sys_timer(void); 160 161 /* PM utility functions */ 162 int arm_validate_power_state(unsigned int power_state, 163 psci_power_state_t *req_state); 164 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 165 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 166 void arm_system_pwr_domain_save(void); 167 void arm_system_pwr_domain_resume(void); 168 void arm_program_trusted_mailbox(uintptr_t address); 169 int arm_psci_read_mem_protect(int *enabled); 170 int arm_nor_psci_write_mem_protect(int val); 171 void arm_nor_psci_do_static_mem_protect(void); 172 void arm_nor_psci_do_dyn_mem_protect(void); 173 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 174 175 /* Topology utility function */ 176 int arm_check_mpidr(u_register_t mpidr); 177 178 /* BL1 utility functions */ 179 void arm_bl1_early_platform_setup(void); 180 void arm_bl1_platform_setup(void); 181 void arm_bl1_plat_arch_setup(void); 182 183 /* BL2 utility functions */ 184 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 185 void arm_bl2_platform_setup(void); 186 void arm_bl2_plat_arch_setup(void); 187 uint32_t arm_get_spsr_for_bl32_entry(void); 188 uint32_t arm_get_spsr_for_bl33_entry(void); 189 int arm_bl2_handle_post_image_load(unsigned int image_id); 190 191 /* BL2 at EL3 functions */ 192 void arm_bl2_el3_early_platform_setup(void); 193 void arm_bl2_el3_plat_arch_setup(void); 194 195 /* BL2U utility functions */ 196 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 197 void *plat_info); 198 void arm_bl2u_platform_setup(void); 199 void arm_bl2u_plat_arch_setup(void); 200 201 /* BL31 utility functions */ 202 #if LOAD_IMAGE_V2 203 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 204 uintptr_t hw_config, void *plat_params_from_bl2); 205 #else 206 void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config, 207 uintptr_t hw_config, void *plat_params_from_bl2); 208 #endif /* LOAD_IMAGE_V2 */ 209 void arm_bl31_platform_setup(void); 210 void arm_bl31_plat_runtime_setup(void); 211 void arm_bl31_plat_arch_setup(void); 212 213 /* TSP utility functions */ 214 void arm_tsp_early_platform_setup(void); 215 216 /* SP_MIN utility functions */ 217 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 218 uintptr_t hw_config, void *plat_params_from_bl2); 219 void arm_sp_min_plat_runtime_setup(void); 220 221 /* FIP TOC validity check */ 222 int arm_io_is_toc_valid(void); 223 224 /* Utility functions for Dynamic Config */ 225 void arm_load_tb_fw_config(void); 226 void arm_bl2_set_tb_cfg_addr(void *dtb); 227 void arm_bl2_dyn_cfg_init(void); 228 229 /* 230 * Mandatory functions required in ARM standard platforms 231 */ 232 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 233 void plat_arm_gic_driver_init(void); 234 void plat_arm_gic_init(void); 235 void plat_arm_gic_cpuif_enable(void); 236 void plat_arm_gic_cpuif_disable(void); 237 void plat_arm_gic_redistif_on(void); 238 void plat_arm_gic_redistif_off(void); 239 void plat_arm_gic_pcpu_init(void); 240 void plat_arm_gic_save(void); 241 void plat_arm_gic_resume(void); 242 void plat_arm_security_setup(void); 243 void plat_arm_pwrc_setup(void); 244 void plat_arm_interconnect_init(void); 245 void plat_arm_interconnect_enter_coherency(void); 246 void plat_arm_interconnect_exit_coherency(void); 247 248 #if ARM_PLAT_MT 249 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 250 #endif 251 252 #if LOAD_IMAGE_V2 253 /* 254 * This function is called after loading SCP_BL2 image and it is used to perform 255 * any platform-specific actions required to handle the SCP firmware. 256 */ 257 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 258 #endif 259 260 /* 261 * Optional functions required in ARM standard platforms 262 */ 263 void plat_arm_io_setup(void); 264 int plat_arm_get_alt_image_source( 265 unsigned int image_id, 266 uintptr_t *dev_handle, 267 uintptr_t *image_spec); 268 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 269 const mmap_region_t *plat_arm_get_mmap(void); 270 271 /* Allow platform to override psci_pm_ops during runtime */ 272 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 273 274 /* Execution state switch in ARM platforms */ 275 int arm_execution_state_switch(unsigned int smc_fid, 276 uint32_t pc_hi, 277 uint32_t pc_lo, 278 uint32_t cookie_hi, 279 uint32_t cookie_lo, 280 void *handle); 281 282 /* Optional functions for SP_MIN */ 283 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 284 u_register_t arg2, u_register_t arg3); 285 286 /* global variables */ 287 extern plat_psci_ops_t plat_arm_psci_pm_ops; 288 extern const mmap_region_t plat_arm_mmap[]; 289 290 #endif /* __PLAT_ARM_H__ */ 291