1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <delay_timer.h> 11 #include <m0_ctl.h> 12 #include <mmio.h> 13 #include <plat_private.h> 14 #include <rk3399_def.h> 15 #include <secure.h> 16 #include <soc.h> 17 18 void m0_init(void) 19 { 20 /* secure config for M0 */ 21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); 22 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); 23 24 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 25 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); 26 27 /* 28 * To switch the parent to xin24M and div == 1, 29 * 30 * We need to close most of the PLLs and clocks except the OSC 24MHz 31 * durning suspend, and this should be enough to supplies the ddrfreq, 32 * For the simple handle, we just keep the fixed 24MHz to supply the 33 * suspend and ddrfreq directly. 34 */ 35 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, 36 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); 37 38 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); 39 } 40 41 void m0_configure_execute_addr(uintptr_t addr) 42 { 43 /* set the execute address for M0 */ 44 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), 45 BITS_WITH_WMASK((addr >> 12) & 0xffff, 46 0xffff, 0)); 47 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), 48 BITS_WITH_WMASK((addr >> 28) & 0xf, 49 0xf, 0)); 50 } 51 52 void m0_start(void) 53 { 54 /* enable clocks for M0 */ 55 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 56 BITS_WITH_WMASK(0x0, 0xf, 0)); 57 58 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ 59 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); 60 dmbst(); 61 62 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 63 BITS_WITH_WMASK(0x0, 0x4, 0)); 64 65 udelay(5); 66 /* start M0 */ 67 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 68 BITS_WITH_WMASK(0x0, 0x20, 0)); 69 dmbst(); 70 } 71 72 void m0_stop(void) 73 { 74 /* stop M0 */ 75 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, 76 BITS_WITH_WMASK(0x24, 0x24, 0)); 77 78 /* disable clocks for M0 */ 79 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, 80 BITS_WITH_WMASK(0xf, 0xf, 0)); 81 } 82 83 void m0_wait_done(void) 84 { 85 do { 86 /* 87 * Don't starve the M0 for access to SRAM, so delay before 88 * reading the PARAM_M0_DONE value again. 89 */ 90 udelay(5); 91 dsb(); 92 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG); 93 94 /* 95 * Let the M0 settle into WFI before we leave. This is so we don't reset 96 * the M0 in a bad spot which can cause problems with the M0. 97 */ 98 udelay(10); 99 dsb(); 100 } 101