1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <interrupt_props.h> 13 #include <spinlock.h> 14 #include "gicv3_private.h" 15 16 const gicv3_driver_data_t *gicv3_driver_data; 17 static unsigned int gicv2_compat; 18 19 /* 20 * Spinlock to guard registers needing read-modify-write. APIs protected by this 21 * spinlock are used either at boot time (when only a single CPU is active), or 22 * when the system is fully coherent. 23 */ 24 static spinlock_t gic_lock; 25 26 /* 27 * Redistributor power operations are weakly bound so that they can be 28 * overridden 29 */ 30 #pragma weak gicv3_rdistif_off 31 #pragma weak gicv3_rdistif_on 32 33 34 /* Helper macros to save and restore GICD registers to and from the context */ 35 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 38 int_id += (1 << REG##_SHIFT)) { \ 39 gicd_write_##reg(base, int_id, \ 40 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 41 } \ 42 } while (0) 43 44 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 45 do { \ 46 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 47 int_id += (1 << REG##_SHIFT)) { \ 48 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 49 gicd_read_##reg(base, int_id); \ 50 } \ 51 } while (0) 52 53 54 /******************************************************************************* 55 * This function initialises the ARM GICv3 driver in EL3 with provided platform 56 * inputs. 57 ******************************************************************************/ 58 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 59 { 60 unsigned int gic_version; 61 62 assert(plat_driver_data); 63 assert(plat_driver_data->gicd_base); 64 assert(plat_driver_data->gicr_base); 65 assert(plat_driver_data->rdistif_num); 66 assert(plat_driver_data->rdistif_base_addrs); 67 68 assert(IS_IN_EL3()); 69 70 #if !ERROR_DEPRECATED 71 if (plat_driver_data->interrupt_props == NULL) { 72 /* Interrupt properties array size must be 0 */ 73 assert(plat_driver_data->interrupt_props_num == 0); 74 75 /* 76 * Suppress deprecated declaration warnings in compatibility 77 * function 78 */ 79 #pragma GCC diagnostic push 80 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 81 82 /* 83 * The platform should provide a list of at least one type of 84 * interrupt. 85 */ 86 assert(plat_driver_data->g0_interrupt_array || 87 plat_driver_data->g1s_interrupt_array); 88 89 /* 90 * If there are no interrupts of a particular type, then the 91 * number of interrupts of that type should be 0 and vice-versa. 92 */ 93 assert(plat_driver_data->g0_interrupt_array ? 94 plat_driver_data->g0_interrupt_num : 95 plat_driver_data->g0_interrupt_num == 0); 96 assert(plat_driver_data->g1s_interrupt_array ? 97 plat_driver_data->g1s_interrupt_num : 98 plat_driver_data->g1s_interrupt_num == 0); 99 #pragma GCC diagnostic pop 100 101 WARN("Using deprecated integer interrupt arrays in " 102 "gicv3_driver_data_t\n"); 103 WARN("Please migrate to using interrupt_prop_t arrays\n"); 104 } 105 #else 106 assert(plat_driver_data->interrupt_props_num > 0 ? 107 plat_driver_data->interrupt_props != NULL : 1); 108 #endif 109 110 /* Check for system register support */ 111 #ifdef AARCH32 112 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 113 #else 114 assert(read_id_aa64pfr0_el1() & 115 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 116 #endif /* AARCH32 */ 117 118 /* The GIC version should be 3.0 */ 119 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 120 gic_version >>= PIDR2_ARCH_REV_SHIFT; 121 gic_version &= PIDR2_ARCH_REV_MASK; 122 assert(gic_version == ARCH_REV_GICV3); 123 124 /* 125 * Find out whether the GIC supports the GICv2 compatibility mode. The 126 * ARE_S bit resets to 0 if supported 127 */ 128 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 129 gicv2_compat >>= CTLR_ARE_S_SHIFT; 130 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 131 132 /* 133 * Find the base address of each implemented Redistributor interface. 134 * The number of interfaces should be equal to the number of CPUs in the 135 * system. The memory for saving these addresses has to be allocated by 136 * the platform port 137 */ 138 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 139 plat_driver_data->rdistif_num, 140 plat_driver_data->gicr_base, 141 plat_driver_data->mpidr_to_core_pos); 142 143 gicv3_driver_data = plat_driver_data; 144 145 /* 146 * The GIC driver data is initialized by the primary CPU with caches 147 * enabled. When the secondary CPU boots up, it initializes the 148 * GICC/GICR interface with the caches disabled. Hence flush the 149 * driver data to ensure coherency. This is not required if the 150 * platform has HW_ASSISTED_COHERENCY enabled. 151 */ 152 #if !HW_ASSISTED_COHERENCY 153 flush_dcache_range((uintptr_t) &gicv3_driver_data, 154 sizeof(gicv3_driver_data)); 155 flush_dcache_range((uintptr_t) gicv3_driver_data, 156 sizeof(*gicv3_driver_data)); 157 #endif 158 159 INFO("GICv3 %s legacy support detected." 160 " ARM GICV3 driver initialized in EL3\n", 161 gicv2_compat ? "with" : "without"); 162 } 163 164 /******************************************************************************* 165 * This function initialises the GIC distributor interface based upon the data 166 * provided by the platform while initialising the driver. 167 ******************************************************************************/ 168 void gicv3_distif_init(void) 169 { 170 unsigned int bitmap = 0; 171 172 assert(gicv3_driver_data); 173 assert(gicv3_driver_data->gicd_base); 174 175 assert(IS_IN_EL3()); 176 177 /* 178 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 179 * the ARE_S bit. The Distributor might generate a system error 180 * otherwise. 181 */ 182 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 183 CTLR_ENABLE_G0_BIT | 184 CTLR_ENABLE_G1S_BIT | 185 CTLR_ENABLE_G1NS_BIT, 186 RWP_TRUE); 187 188 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 189 gicd_set_ctlr(gicv3_driver_data->gicd_base, 190 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 191 192 /* Set the default attribute of all SPIs */ 193 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 194 195 #if !ERROR_DEPRECATED 196 if (gicv3_driver_data->interrupt_props != NULL) { 197 #endif 198 bitmap = gicv3_secure_spis_config_props( 199 gicv3_driver_data->gicd_base, 200 gicv3_driver_data->interrupt_props, 201 gicv3_driver_data->interrupt_props_num); 202 #if !ERROR_DEPRECATED 203 } else { 204 /* 205 * Suppress deprecated declaration warnings in compatibility 206 * function 207 */ 208 #pragma GCC diagnostic push 209 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 210 211 assert(gicv3_driver_data->g1s_interrupt_array || 212 gicv3_driver_data->g0_interrupt_array); 213 214 /* Configure the G1S SPIs */ 215 if (gicv3_driver_data->g1s_interrupt_array) { 216 gicv3_secure_spis_config(gicv3_driver_data->gicd_base, 217 gicv3_driver_data->g1s_interrupt_num, 218 gicv3_driver_data->g1s_interrupt_array, 219 INTR_GROUP1S); 220 bitmap |= CTLR_ENABLE_G1S_BIT; 221 } 222 223 /* Configure the G0 SPIs */ 224 if (gicv3_driver_data->g0_interrupt_array) { 225 gicv3_secure_spis_config(gicv3_driver_data->gicd_base, 226 gicv3_driver_data->g0_interrupt_num, 227 gicv3_driver_data->g0_interrupt_array, 228 INTR_GROUP0); 229 bitmap |= CTLR_ENABLE_G0_BIT; 230 } 231 #pragma GCC diagnostic pop 232 } 233 #endif 234 235 /* Enable the secure SPIs now that they have been configured */ 236 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 237 } 238 239 /******************************************************************************* 240 * This function initialises the GIC Redistributor interface of the calling CPU 241 * (identified by the 'proc_num' parameter) based upon the data provided by the 242 * platform while initialising the driver. 243 ******************************************************************************/ 244 void gicv3_rdistif_init(unsigned int proc_num) 245 { 246 uintptr_t gicr_base; 247 unsigned int bitmap = 0; 248 uint32_t ctlr; 249 250 assert(gicv3_driver_data); 251 assert(proc_num < gicv3_driver_data->rdistif_num); 252 assert(gicv3_driver_data->rdistif_base_addrs); 253 assert(gicv3_driver_data->gicd_base); 254 255 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 256 assert(ctlr & CTLR_ARE_S_BIT); 257 258 assert(IS_IN_EL3()); 259 260 /* Power on redistributor */ 261 gicv3_rdistif_on(proc_num); 262 263 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 264 265 /* Set the default attribute of all SGIs and PPIs */ 266 gicv3_ppi_sgi_config_defaults(gicr_base); 267 268 #if !ERROR_DEPRECATED 269 if (gicv3_driver_data->interrupt_props != NULL) { 270 #endif 271 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 272 gicv3_driver_data->interrupt_props, 273 gicv3_driver_data->interrupt_props_num); 274 #if !ERROR_DEPRECATED 275 } else { 276 /* 277 * Suppress deprecated declaration warnings in compatibility 278 * function 279 */ 280 #pragma GCC diagnostic push 281 #pragma GCC diagnostic ignored "-Wdeprecated-declarations" 282 283 assert(gicv3_driver_data->g1s_interrupt_array || 284 gicv3_driver_data->g0_interrupt_array); 285 286 /* Configure the G1S SGIs/PPIs */ 287 if (gicv3_driver_data->g1s_interrupt_array) { 288 gicv3_secure_ppi_sgi_config(gicr_base, 289 gicv3_driver_data->g1s_interrupt_num, 290 gicv3_driver_data->g1s_interrupt_array, 291 INTR_GROUP1S); 292 bitmap |= CTLR_ENABLE_G1S_BIT; 293 } 294 295 /* Configure the G0 SGIs/PPIs */ 296 if (gicv3_driver_data->g0_interrupt_array) { 297 gicv3_secure_ppi_sgi_config(gicr_base, 298 gicv3_driver_data->g0_interrupt_num, 299 gicv3_driver_data->g0_interrupt_array, 300 INTR_GROUP0); 301 bitmap |= CTLR_ENABLE_G0_BIT; 302 } 303 #pragma GCC diagnostic pop 304 } 305 #endif 306 307 /* Enable interrupt groups as required, if not already */ 308 if ((ctlr & bitmap) != bitmap) 309 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 310 } 311 312 /******************************************************************************* 313 * Functions to perform power operations on GIC Redistributor 314 ******************************************************************************/ 315 void gicv3_rdistif_off(unsigned int proc_num) 316 { 317 return; 318 } 319 320 void gicv3_rdistif_on(unsigned int proc_num) 321 { 322 return; 323 } 324 325 /******************************************************************************* 326 * This function enables the GIC CPU interface of the calling CPU using only 327 * system register accesses. 328 ******************************************************************************/ 329 void gicv3_cpuif_enable(unsigned int proc_num) 330 { 331 uintptr_t gicr_base; 332 unsigned int scr_el3; 333 unsigned int icc_sre_el3; 334 335 assert(gicv3_driver_data); 336 assert(proc_num < gicv3_driver_data->rdistif_num); 337 assert(gicv3_driver_data->rdistif_base_addrs); 338 assert(IS_IN_EL3()); 339 340 /* Mark the connected core as awake */ 341 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 342 gicv3_rdistif_mark_core_awake(gicr_base); 343 344 /* Disable the legacy interrupt bypass */ 345 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 346 347 /* 348 * Enable system register access for EL3 and allow lower exception 349 * levels to configure the same for themselves. If the legacy mode is 350 * not supported, the SRE bit is RAO/WI 351 */ 352 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 353 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 354 355 scr_el3 = read_scr_el3(); 356 357 /* 358 * Switch to NS state to write Non secure ICC_SRE_EL1 and 359 * ICC_SRE_EL2 registers. 360 */ 361 write_scr_el3(scr_el3 | SCR_NS_BIT); 362 isb(); 363 364 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 365 write_icc_sre_el1(ICC_SRE_SRE_BIT); 366 isb(); 367 368 /* Switch to secure state. */ 369 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 370 isb(); 371 372 /* Program the idle priority in the PMR */ 373 write_icc_pmr_el1(GIC_PRI_MASK); 374 375 /* Enable Group0 interrupts */ 376 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 377 378 /* Enable Group1 Secure interrupts */ 379 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 380 IGRPEN1_EL3_ENABLE_G1S_BIT); 381 382 /* Write the secure ICC_SRE_EL1 register */ 383 write_icc_sre_el1(ICC_SRE_SRE_BIT); 384 isb(); 385 } 386 387 /******************************************************************************* 388 * This function disables the GIC CPU interface of the calling CPU using 389 * only system register accesses. 390 ******************************************************************************/ 391 void gicv3_cpuif_disable(unsigned int proc_num) 392 { 393 uintptr_t gicr_base; 394 395 assert(gicv3_driver_data); 396 assert(proc_num < gicv3_driver_data->rdistif_num); 397 assert(gicv3_driver_data->rdistif_base_addrs); 398 399 assert(IS_IN_EL3()); 400 401 /* Disable legacy interrupt bypass */ 402 write_icc_sre_el3(read_icc_sre_el3() | 403 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 404 405 /* Disable Group0 interrupts */ 406 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 407 ~IGRPEN1_EL1_ENABLE_G0_BIT); 408 409 /* Disable Group1 Secure and Non-Secure interrupts */ 410 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 411 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 412 IGRPEN1_EL3_ENABLE_G1S_BIT)); 413 414 /* Synchronise accesses to group enable registers */ 415 isb(); 416 417 /* Mark the connected core as asleep */ 418 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 419 gicv3_rdistif_mark_core_asleep(gicr_base); 420 } 421 422 /******************************************************************************* 423 * This function returns the id of the highest priority pending interrupt at 424 * the GIC cpu interface. 425 ******************************************************************************/ 426 unsigned int gicv3_get_pending_interrupt_id(void) 427 { 428 unsigned int id; 429 430 assert(IS_IN_EL3()); 431 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 432 433 /* 434 * If the ID is special identifier corresponding to G1S or G1NS 435 * interrupt, then read the highest pending group 1 interrupt. 436 */ 437 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 438 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 439 440 return id; 441 } 442 443 /******************************************************************************* 444 * This function returns the type of the highest priority pending interrupt at 445 * the GIC cpu interface. The return values can be one of the following : 446 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 447 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 448 * 0 - 1019 : The interrupt type is secure Group 0. 449 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 450 * sufficient priority to be signaled 451 ******************************************************************************/ 452 unsigned int gicv3_get_pending_interrupt_type(void) 453 { 454 assert(IS_IN_EL3()); 455 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 456 } 457 458 /******************************************************************************* 459 * This function returns the type of the interrupt id depending upon the group 460 * this interrupt has been configured under by the interrupt controller i.e. 461 * group0 or group1 Secure / Non Secure. The return value can be one of the 462 * following : 463 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 464 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 465 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 466 * interrupt. 467 ******************************************************************************/ 468 unsigned int gicv3_get_interrupt_type(unsigned int id, 469 unsigned int proc_num) 470 { 471 unsigned int igroup, grpmodr; 472 uintptr_t gicr_base; 473 474 assert(IS_IN_EL3()); 475 assert(gicv3_driver_data); 476 477 /* Ensure the parameters are valid */ 478 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 479 assert(proc_num < gicv3_driver_data->rdistif_num); 480 481 /* All LPI interrupts are Group 1 non secure */ 482 if (id >= MIN_LPI_ID) 483 return INTR_GROUP1NS; 484 485 if (id < MIN_SPI_ID) { 486 assert(gicv3_driver_data->rdistif_base_addrs); 487 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 488 igroup = gicr_get_igroupr0(gicr_base, id); 489 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 490 } else { 491 assert(gicv3_driver_data->gicd_base); 492 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 493 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 494 } 495 496 /* 497 * If the IGROUP bit is set, then it is a Group 1 Non secure 498 * interrupt 499 */ 500 if (igroup) 501 return INTR_GROUP1NS; 502 503 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 504 if (grpmodr) 505 return INTR_GROUP1S; 506 507 /* Else it is a Group 0 Secure interrupt */ 508 return INTR_GROUP0; 509 } 510 511 /***************************************************************************** 512 * Function to save and disable the GIC ITS register context. The power 513 * management of GIC ITS is implementation-defined and this function doesn't 514 * save any memory structures required to support ITS. As the sequence to save 515 * this state is implementation defined, it should be executed in platform 516 * specific code. Calling this function alone and then powering down the GIC and 517 * ITS without implementing the aforementioned platform specific code will 518 * corrupt the ITS state. 519 * 520 * This function must be invoked after the GIC CPU interface is disabled. 521 *****************************************************************************/ 522 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 523 { 524 int i; 525 526 assert(gicv3_driver_data); 527 assert(IS_IN_EL3()); 528 assert(its_ctx); 529 assert(gits_base); 530 531 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 532 533 /* Disable the ITS */ 534 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 535 (~GITS_CTLR_ENABLED_BIT)); 536 537 /* Wait for quiescent state */ 538 gits_wait_for_quiescent_bit(gits_base); 539 540 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 541 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 542 543 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 544 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 545 } 546 547 /***************************************************************************** 548 * Function to restore the GIC ITS register context. The power 549 * management of GIC ITS is implementation defined and this function doesn't 550 * restore any memory structures required to support ITS. The assumption is 551 * that these structures are in memory and are retained during system suspend. 552 * 553 * This must be invoked before the GIC CPU interface is enabled. 554 *****************************************************************************/ 555 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 556 { 557 int i; 558 559 assert(gicv3_driver_data); 560 assert(IS_IN_EL3()); 561 assert(its_ctx); 562 assert(gits_base); 563 564 /* Assert that the GITS is disabled and quiescent */ 565 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0); 566 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0); 567 568 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 569 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 570 571 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 572 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 573 574 /* Restore the ITS CTLR but leave the ITS disabled */ 575 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 576 (~GITS_CTLR_ENABLED_BIT)); 577 } 578 579 /***************************************************************************** 580 * Function to save the GIC Redistributor register context. This function 581 * must be invoked after CPU interface disable and prior to Distributor save. 582 *****************************************************************************/ 583 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 584 { 585 uintptr_t gicr_base; 586 unsigned int int_id; 587 588 assert(gicv3_driver_data); 589 assert(proc_num < gicv3_driver_data->rdistif_num); 590 assert(gicv3_driver_data->rdistif_base_addrs); 591 assert(IS_IN_EL3()); 592 assert(rdist_ctx); 593 594 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 595 596 /* 597 * Wait for any write to GICR_CTLR to complete before trying to save any 598 * state. 599 */ 600 gicr_wait_for_pending_write(gicr_base); 601 602 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 603 604 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 605 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 606 607 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 608 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 609 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 610 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 611 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 612 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 613 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 614 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 615 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 616 int_id += (1 << IPRIORITYR_SHIFT)) { 617 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 618 gicr_read_ipriorityr(gicr_base, int_id); 619 } 620 621 622 /* 623 * Call the pre-save hook that implements the IMP DEF sequence that may 624 * be required on some GIC implementations. As this may need to access 625 * the Redistributor registers, we pass it proc_num. 626 */ 627 gicv3_distif_pre_save(proc_num); 628 } 629 630 /***************************************************************************** 631 * Function to restore the GIC Redistributor register context. We disable 632 * LPI and per-cpu interrupts before we start restore of the Redistributor. 633 * This function must be invoked after Distributor restore but prior to 634 * CPU interface enable. The pending and active interrupts are restored 635 * after the interrupts are fully configured and enabled. 636 *****************************************************************************/ 637 void gicv3_rdistif_init_restore(unsigned int proc_num, 638 const gicv3_redist_ctx_t * const rdist_ctx) 639 { 640 uintptr_t gicr_base; 641 unsigned int int_id; 642 643 assert(gicv3_driver_data); 644 assert(proc_num < gicv3_driver_data->rdistif_num); 645 assert(gicv3_driver_data->rdistif_base_addrs); 646 assert(IS_IN_EL3()); 647 assert(rdist_ctx); 648 649 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 650 651 /* Power on redistributor */ 652 gicv3_rdistif_on(proc_num); 653 654 /* 655 * Call the post-restore hook that implements the IMP DEF sequence that 656 * may be required on some GIC implementations. As this may need to 657 * access the Redistributor registers, we pass it proc_num. 658 */ 659 gicv3_distif_post_restore(proc_num); 660 661 /* 662 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 663 * more scalable approach as it avoids clearing the enable bits in the 664 * GICD_CTLR 665 */ 666 gicr_write_icenabler0(gicr_base, ~0); 667 /* Wait for pending writes to GICR_ICENABLER */ 668 gicr_wait_for_pending_write(gicr_base); 669 670 /* 671 * Disable the LPIs to avoid unpredictable behavior when writing to 672 * GICR_PROPBASER and GICR_PENDBASER. 673 */ 674 gicr_write_ctlr(gicr_base, 675 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 676 677 /* Restore registers' content */ 678 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 679 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 680 681 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 682 683 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 684 int_id += (1 << IPRIORITYR_SHIFT)) { 685 gicr_write_ipriorityr(gicr_base, int_id, 686 rdist_ctx->gicr_ipriorityr[ 687 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 688 } 689 690 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 691 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 692 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 693 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 694 695 /* Restore after group and priorities are set */ 696 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 697 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 698 699 /* 700 * Wait for all writes to the Distributor to complete before enabling 701 * the SGI and PPIs. 702 */ 703 gicr_wait_for_upstream_pending_write(gicr_base); 704 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 705 706 /* 707 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 708 * the first write to GICR_CTLR was still in flight (this write only 709 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 710 * bit). 711 */ 712 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 713 gicr_wait_for_pending_write(gicr_base); 714 } 715 716 /***************************************************************************** 717 * Function to save the GIC Distributor register context. This function 718 * must be invoked after CPU interface disable and Redistributor save. 719 *****************************************************************************/ 720 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 721 { 722 unsigned int num_ints; 723 724 assert(gicv3_driver_data); 725 assert(gicv3_driver_data->gicd_base); 726 assert(IS_IN_EL3()); 727 assert(dist_ctx); 728 729 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 730 731 num_ints = gicd_read_typer(gicd_base); 732 num_ints &= TYPER_IT_LINES_NO_MASK; 733 num_ints = (num_ints + 1) << 5; 734 735 assert(num_ints <= MAX_SPI_ID + 1); 736 737 /* Wait for pending write to complete */ 738 gicd_wait_for_pending_write(gicd_base); 739 740 /* Save the GICD_CTLR */ 741 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 742 743 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 744 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 745 746 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 747 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 748 749 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 750 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 751 752 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 753 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 754 755 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 756 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 757 758 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 759 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 760 761 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 762 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 763 764 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 765 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 766 767 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 768 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 769 770 /* 771 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 772 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 773 * driver. 774 */ 775 } 776 777 /***************************************************************************** 778 * Function to restore the GIC Distributor register context. We disable G0, G1S 779 * and G1NS interrupt groups before we start restore of the Distributor. This 780 * function must be invoked prior to Redistributor restore and CPU interface 781 * enable. The pending and active interrupts are restored after the interrupts 782 * are fully configured and enabled. 783 *****************************************************************************/ 784 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 785 { 786 unsigned int num_ints = 0; 787 788 assert(gicv3_driver_data); 789 assert(gicv3_driver_data->gicd_base); 790 assert(IS_IN_EL3()); 791 assert(dist_ctx); 792 793 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 794 795 /* 796 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 797 * the ARE_S bit. The Distributor might generate a system error 798 * otherwise. 799 */ 800 gicd_clr_ctlr(gicd_base, 801 CTLR_ENABLE_G0_BIT | 802 CTLR_ENABLE_G1S_BIT | 803 CTLR_ENABLE_G1NS_BIT, 804 RWP_TRUE); 805 806 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 807 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 808 809 num_ints = gicd_read_typer(gicd_base); 810 num_ints &= TYPER_IT_LINES_NO_MASK; 811 num_ints = (num_ints + 1) << 5; 812 813 assert(num_ints <= MAX_SPI_ID + 1); 814 815 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 816 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 817 818 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 819 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 820 821 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 822 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 823 824 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 825 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 826 827 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 828 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 829 830 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 831 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 832 833 /* 834 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 835 * configured. 836 */ 837 838 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 839 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 840 841 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 842 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 843 844 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 845 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 846 847 /* Restore the GICD_CTLR */ 848 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 849 gicd_wait_for_pending_write(gicd_base); 850 851 } 852 853 /******************************************************************************* 854 * This function gets the priority of the interrupt the processor is currently 855 * servicing. 856 ******************************************************************************/ 857 unsigned int gicv3_get_running_priority(void) 858 { 859 return read_icc_rpr_el1(); 860 } 861 862 /******************************************************************************* 863 * This function checks if the interrupt identified by id is active (whether the 864 * state is either active, or active and pending). The proc_num is used if the 865 * interrupt is SGI or PPI and programs the corresponding Redistributor 866 * interface. 867 ******************************************************************************/ 868 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 869 { 870 unsigned int value; 871 872 assert(gicv3_driver_data); 873 assert(gicv3_driver_data->gicd_base); 874 assert(proc_num < gicv3_driver_data->rdistif_num); 875 assert(gicv3_driver_data->rdistif_base_addrs); 876 assert(id <= MAX_SPI_ID); 877 878 if (id < MIN_SPI_ID) { 879 /* For SGIs and PPIs */ 880 value = gicr_get_isactiver0( 881 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 882 } else { 883 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 884 } 885 886 return value; 887 } 888 889 /******************************************************************************* 890 * This function enables the interrupt identified by id. The proc_num 891 * is used if the interrupt is SGI or PPI, and programs the corresponding 892 * Redistributor interface. 893 ******************************************************************************/ 894 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 895 { 896 assert(gicv3_driver_data); 897 assert(gicv3_driver_data->gicd_base); 898 assert(proc_num < gicv3_driver_data->rdistif_num); 899 assert(gicv3_driver_data->rdistif_base_addrs); 900 assert(id <= MAX_SPI_ID); 901 902 /* 903 * Ensure that any shared variable updates depending on out of band 904 * interrupt trigger are observed before enabling interrupt. 905 */ 906 dsbishst(); 907 if (id < MIN_SPI_ID) { 908 /* For SGIs and PPIs */ 909 gicr_set_isenabler0( 910 gicv3_driver_data->rdistif_base_addrs[proc_num], 911 id); 912 } else { 913 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 914 } 915 } 916 917 /******************************************************************************* 918 * This function disables the interrupt identified by id. The proc_num 919 * is used if the interrupt is SGI or PPI, and programs the corresponding 920 * Redistributor interface. 921 ******************************************************************************/ 922 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 923 { 924 assert(gicv3_driver_data); 925 assert(gicv3_driver_data->gicd_base); 926 assert(proc_num < gicv3_driver_data->rdistif_num); 927 assert(gicv3_driver_data->rdistif_base_addrs); 928 assert(id <= MAX_SPI_ID); 929 930 /* 931 * Disable interrupt, and ensure that any shared variable updates 932 * depending on out of band interrupt trigger are observed afterwards. 933 */ 934 if (id < MIN_SPI_ID) { 935 /* For SGIs and PPIs */ 936 gicr_set_icenabler0( 937 gicv3_driver_data->rdistif_base_addrs[proc_num], 938 id); 939 940 /* Write to clear enable requires waiting for pending writes */ 941 gicr_wait_for_pending_write( 942 gicv3_driver_data->rdistif_base_addrs[proc_num]); 943 } else { 944 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 945 946 /* Write to clear enable requires waiting for pending writes */ 947 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 948 } 949 950 dsbishst(); 951 } 952 953 /******************************************************************************* 954 * This function sets the interrupt priority as supplied for the given interrupt 955 * id. 956 ******************************************************************************/ 957 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 958 unsigned int priority) 959 { 960 uintptr_t gicr_base; 961 962 assert(gicv3_driver_data); 963 assert(gicv3_driver_data->gicd_base); 964 assert(proc_num < gicv3_driver_data->rdistif_num); 965 assert(gicv3_driver_data->rdistif_base_addrs); 966 assert(id <= MAX_SPI_ID); 967 968 if (id < MIN_SPI_ID) { 969 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 970 gicr_set_ipriorityr(gicr_base, id, priority); 971 } else { 972 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 973 } 974 } 975 976 /******************************************************************************* 977 * This function assigns group for the interrupt identified by id. The proc_num 978 * is used if the interrupt is SGI or PPI, and programs the corresponding 979 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 980 ******************************************************************************/ 981 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 982 unsigned int type) 983 { 984 unsigned int igroup = 0, grpmod = 0; 985 uintptr_t gicr_base; 986 987 assert(gicv3_driver_data); 988 assert(gicv3_driver_data->gicd_base); 989 assert(proc_num < gicv3_driver_data->rdistif_num); 990 assert(gicv3_driver_data->rdistif_base_addrs); 991 992 switch (type) { 993 case INTR_GROUP1S: 994 igroup = 0; 995 grpmod = 1; 996 break; 997 case INTR_GROUP0: 998 igroup = 0; 999 grpmod = 0; 1000 break; 1001 case INTR_GROUP1NS: 1002 igroup = 1; 1003 grpmod = 0; 1004 break; 1005 default: 1006 assert(0); 1007 break; 1008 } 1009 1010 if (id < MIN_SPI_ID) { 1011 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1012 if (igroup) 1013 gicr_set_igroupr0(gicr_base, id); 1014 else 1015 gicr_clr_igroupr0(gicr_base, id); 1016 1017 if (grpmod) 1018 gicr_set_igrpmodr0(gicr_base, id); 1019 else 1020 gicr_clr_igrpmodr0(gicr_base, id); 1021 } else { 1022 /* Serialize read-modify-write to Distributor registers */ 1023 spin_lock(&gic_lock); 1024 if (igroup) 1025 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 1026 else 1027 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1028 1029 if (grpmod) 1030 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 1031 else 1032 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1033 spin_unlock(&gic_lock); 1034 } 1035 } 1036 1037 /******************************************************************************* 1038 * This function raises the specified Secure Group 0 SGI. 1039 * 1040 * The target parameter must be a valid MPIDR in the system. 1041 ******************************************************************************/ 1042 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target) 1043 { 1044 unsigned int tgt, aff3, aff2, aff1, aff0; 1045 uint64_t sgi_val; 1046 1047 /* Verify interrupt number is in the SGI range */ 1048 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1049 1050 /* Extract affinity fields from target */ 1051 aff0 = MPIDR_AFFLVL0_VAL(target); 1052 aff1 = MPIDR_AFFLVL1_VAL(target); 1053 aff2 = MPIDR_AFFLVL2_VAL(target); 1054 aff3 = MPIDR_AFFLVL3_VAL(target); 1055 1056 /* 1057 * Make target list from affinity 0, and ensure GICv3 SGI can target 1058 * this PE. 1059 */ 1060 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1061 tgt = BIT(aff0); 1062 1063 /* Raise SGI to PE specified by its affinity */ 1064 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1065 tgt); 1066 1067 /* 1068 * Ensure that any shared variable updates depending on out of band 1069 * interrupt trigger are observed before raising SGI. 1070 */ 1071 dsbishst(); 1072 write_icc_sgi0r_el1(sgi_val); 1073 isb(); 1074 } 1075 1076 /******************************************************************************* 1077 * This function sets the interrupt routing for the given SPI interrupt id. 1078 * The interrupt routing is specified in routing mode and mpidr. 1079 * 1080 * The routing mode can be either of: 1081 * - GICV3_IRM_ANY 1082 * - GICV3_IRM_PE 1083 * 1084 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1085 * and is ignored for routing mode GICV3_IRM_ANY. 1086 ******************************************************************************/ 1087 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1088 { 1089 unsigned long long aff; 1090 uint64_t router; 1091 1092 assert(gicv3_driver_data); 1093 assert(gicv3_driver_data->gicd_base); 1094 1095 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1096 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 1097 1098 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1099 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1100 1101 /* 1102 * In implementations that do not require 1 of N distribution of SPIs, 1103 * IRM might be RAZ/WI. Read back and verify IRM bit. 1104 */ 1105 if (irm == GICV3_IRM_ANY) { 1106 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1107 if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) { 1108 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1109 panic(); 1110 } 1111 } 1112 } 1113 1114 /******************************************************************************* 1115 * This function clears the pending status of an interrupt identified by id. 1116 * The proc_num is used if the interrupt is SGI or PPI, and programs the 1117 * corresponding Redistributor interface. 1118 ******************************************************************************/ 1119 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1120 { 1121 assert(gicv3_driver_data); 1122 assert(gicv3_driver_data->gicd_base); 1123 assert(proc_num < gicv3_driver_data->rdistif_num); 1124 assert(gicv3_driver_data->rdistif_base_addrs); 1125 1126 /* 1127 * Clear pending interrupt, and ensure that any shared variable updates 1128 * depending on out of band interrupt trigger are observed afterwards. 1129 */ 1130 if (id < MIN_SPI_ID) { 1131 /* For SGIs and PPIs */ 1132 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1133 id); 1134 } else { 1135 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1136 } 1137 dsbishst(); 1138 } 1139 1140 /******************************************************************************* 1141 * This function sets the pending status of an interrupt identified by id. 1142 * The proc_num is used if the interrupt is SGI or PPI and programs the 1143 * corresponding Redistributor interface. 1144 ******************************************************************************/ 1145 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1146 { 1147 assert(gicv3_driver_data); 1148 assert(gicv3_driver_data->gicd_base); 1149 assert(proc_num < gicv3_driver_data->rdistif_num); 1150 assert(gicv3_driver_data->rdistif_base_addrs); 1151 1152 /* 1153 * Ensure that any shared variable updates depending on out of band 1154 * interrupt trigger are observed before setting interrupt pending. 1155 */ 1156 dsbishst(); 1157 if (id < MIN_SPI_ID) { 1158 /* For SGIs and PPIs */ 1159 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1160 id); 1161 } else { 1162 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1163 } 1164 } 1165 1166 /******************************************************************************* 1167 * This function sets the PMR register with the supplied value. Returns the 1168 * original PMR. 1169 ******************************************************************************/ 1170 unsigned int gicv3_set_pmr(unsigned int mask) 1171 { 1172 unsigned int old_mask; 1173 1174 old_mask = read_icc_pmr_el1(); 1175 1176 /* 1177 * Order memory updates w.r.t. PMR write, and ensure they're visible 1178 * before potential out of band interrupt trigger because of PMR update. 1179 * PMR system register writes are self-synchronizing, so no ISB required 1180 * thereafter. 1181 */ 1182 dsbishst(); 1183 write_icc_pmr_el1(mask); 1184 1185 return old_mask; 1186 } 1187