1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38func cortex_a73_reset_func 39#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 40 cpu_check_csv2 x0, 1f 41 adr x0, wa_cve_2017_5715_bpiall_vbar 42 msr vbar_el3, x0 431: 44#endif 45 46#if WORKAROUND_CVE_2018_3639 47 mrs x0, CORTEX_A73_IMP_DEF_REG1 48 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 49 msr CORTEX_A73_IMP_DEF_REG1, x0 50 isb 51#endif 52 53 /* --------------------------------------------- 54 * Enable the SMP bit. 55 * Clobbers : x0 56 * --------------------------------------------- 57 */ 58 mrs x0, CORTEX_A73_CPUECTLR_EL1 59 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 60 msr CORTEX_A73_CPUECTLR_EL1, x0 61 isb 62 ret 63endfunc cortex_a73_reset_func 64 65func cortex_a73_core_pwr_dwn 66 mov x18, x30 67 68 /* --------------------------------------------- 69 * Turn off caches. 70 * --------------------------------------------- 71 */ 72 bl cortex_a73_disable_dcache 73 74 /* --------------------------------------------- 75 * Flush L1 caches. 76 * --------------------------------------------- 77 */ 78 mov x0, #DCCISW 79 bl dcsw_op_level1 80 81 /* --------------------------------------------- 82 * Come out of intra cluster coherency 83 * --------------------------------------------- 84 */ 85 mov x30, x18 86 b cortex_a73_disable_smp 87endfunc cortex_a73_core_pwr_dwn 88 89func cortex_a73_cluster_pwr_dwn 90 mov x18, x30 91 92 /* --------------------------------------------- 93 * Turn off caches. 94 * --------------------------------------------- 95 */ 96 bl cortex_a73_disable_dcache 97 98 /* --------------------------------------------- 99 * Flush L1 caches. 100 * --------------------------------------------- 101 */ 102 mov x0, #DCCISW 103 bl dcsw_op_level1 104 105 /* --------------------------------------------- 106 * Disable the optional ACP. 107 * --------------------------------------------- 108 */ 109 bl plat_disable_acp 110 111 /* --------------------------------------------- 112 * Flush L2 caches. 113 * --------------------------------------------- 114 */ 115 mov x0, #DCCISW 116 bl dcsw_op_level2 117 118 /* --------------------------------------------- 119 * Come out of intra cluster coherency 120 * --------------------------------------------- 121 */ 122 mov x30, x18 123 b cortex_a73_disable_smp 124endfunc cortex_a73_cluster_pwr_dwn 125 126func check_errata_cve_2017_5715 127 cpu_check_csv2 x0, 1f 128#if WORKAROUND_CVE_2017_5715 129 mov x0, #ERRATA_APPLIES 130#else 131 mov x0, #ERRATA_MISSING 132#endif 133 ret 1341: 135 mov x0, #ERRATA_NOT_APPLIES 136 ret 137endfunc check_errata_cve_2017_5715 138 139func check_errata_cve_2018_3639 140#if WORKAROUND_CVE_2018_3639 141 mov x0, #ERRATA_APPLIES 142#else 143 mov x0, #ERRATA_MISSING 144#endif 145 ret 146endfunc check_errata_cve_2018_3639 147 148#if REPORT_ERRATA 149/* 150 * Errata printing function for Cortex A75. Must follow AAPCS. 151 */ 152func cortex_a73_errata_report 153 stp x8, x30, [sp, #-16]! 154 155 bl cpu_get_rev_var 156 mov x8, x0 157 158 /* 159 * Report all errata. The revision-variant information is passed to 160 * checking functions of each errata. 161 */ 162 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 163 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 164 165 ldp x8, x30, [sp], #16 166 ret 167endfunc cortex_a73_errata_report 168#endif 169 170 /* --------------------------------------------- 171 * This function provides cortex_a73 specific 172 * register information for crash reporting. 173 * It needs to return with x6 pointing to 174 * a list of register names in ascii and 175 * x8 - x15 having values of registers to be 176 * reported. 177 * --------------------------------------------- 178 */ 179.section .rodata.cortex_a73_regs, "aS" 180cortex_a73_regs: /* The ascii list of register names to be reported */ 181 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 182 183func cortex_a73_cpu_reg_dump 184 adr x6, cortex_a73_regs 185 mrs x8, CORTEX_A73_CPUECTLR_EL1 186 mrs x9, CORTEX_A73_L2MERRSR_EL1 187 ret 188endfunc cortex_a73_cpu_reg_dump 189 190declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 191 cortex_a73_reset_func, \ 192 check_errata_cve_2017_5715, \ 193 CPU_NO_EXTRA2_FUNC, \ 194 cortex_a73_core_pwr_dwn, \ 195 cortex_a73_cluster_pwr_dwn 196