1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 #include <arm_def.h> 22 #include <arm_spm_def.h> 23 #include <board_arm_def.h> 24 #include <common_def.h> 25 #include <tzc400.h> 26 #include <utils_def.h> 27 #include <v2m_def.h> 28 #include "../fvp_def.h" 29 30 /* Required platform porting definitions */ 31 #define PLATFORM_CORE_COUNT \ 32 (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) 33 34 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 35 PLATFORM_CORE_COUNT) + 1 36 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 39 /* 40 * Other platform porting definitions are provided by included headers 41 */ 42 43 /* 44 * Required ARM standard platform porting definitions 45 */ 46 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 49 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 53 54 /* virtual address used by dynamic mem_protect for chunk_base */ 55 #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 56 57 /* No SCP in FVP */ 58 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 59 60 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 61 62 /* 63 * Load address of BL33 for this platform port 64 */ 65 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + U(0x8000000)) 66 67 68 /* 69 * PL011 related constants 70 */ 71 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 72 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 73 74 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 75 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 76 77 #define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 78 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 79 80 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 81 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 82 83 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 84 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 85 86 #define PLAT_FVP_SMMUV3_BASE 0x2b400000 87 88 /* CCI related constants */ 89 #define PLAT_FVP_CCI400_BASE 0x2c090000 90 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 91 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 92 93 /* CCI-500/CCI-550 on Base platform */ 94 #define PLAT_FVP_CCI5XX_BASE 0x2a000000 95 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 96 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 97 98 /* CCN related constants. Only CCN 502 is currently supported */ 99 #define PLAT_ARM_CCN_BASE 0x2e000000 100 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 101 102 /* System timer related constants */ 103 #define PLAT_ARM_NSTIMER_FRAME_ID 1 104 105 /* Mailbox base address */ 106 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 107 108 109 /* TrustZone controller related constants 110 * 111 * Currently only filters 0 and 2 are connected on Base FVP. 112 * Filter 0 : CPU clusters (no access to DRAM by default) 113 * Filter 1 : not connected 114 * Filter 2 : LCDs (access to VRAM allowed by default) 115 * Filter 3 : not connected 116 * Programming unconnected filters will have no effect at the 117 * moment. These filter could, however, be connected in future. 118 * So care should be taken not to configure the unused filters. 119 * 120 * Allow only non-secure access to all DRAM to supported devices. 121 * Give access to the CPUs and Virtio. Some devices 122 * would normally use the default ID so allow that too. 123 */ 124 #define PLAT_ARM_TZC_BASE 0x2a4a0000 125 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 126 127 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 128 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 129 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 130 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 131 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 132 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 133 134 /* 135 * GIC related constants to cater for both GICv2 and GICv3 instances of an 136 * FVP. They could be overriden at runtime in case the FVP implements the legacy 137 * VE memory map. 138 */ 139 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 140 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 141 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 142 143 /* 144 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 145 * terminology. On a GICv2 system or mode, the lists will be merged and treated 146 * as Group 0 interrupts. 147 */ 148 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 149 FVP_IRQ_TZ_WDOG, \ 150 FVP_IRQ_SEC_SYS_TIMER 151 152 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 153 154 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 155 ARM_G1S_IRQ_PROPS(grp), \ 156 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 157 GIC_INTR_CFG_LEVEL), \ 158 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 159 GIC_INTR_CFG_LEVEL) 160 161 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 162 163 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 164 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 165 166 #endif /* __PLATFORM_DEF_H__ */ 167