1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 #include <ras.h> 18 19 #define BL31_END (uintptr_t)(&__BL31_END__) 20 21 /* 22 * Placeholder variables for copying the arguments that have been passed to 23 * BL31 from BL2. 24 */ 25 static entry_point_info_t bl32_image_ep_info; 26 static entry_point_info_t bl33_image_ep_info; 27 28 /* 29 * Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 30 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 31 */ 32 CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 33 34 /* Weak definitions may be overridden in specific ARM standard platform */ 35 #pragma weak bl31_early_platform_setup2 36 #pragma weak bl31_platform_setup 37 #pragma weak bl31_plat_arch_setup 38 #pragma weak bl31_plat_get_next_image_ep_info 39 40 41 /******************************************************************************* 42 * Return a pointer to the 'entry_point_info' structure of the next image for the 43 * security state specified. BL33 corresponds to the non-secure image type 44 * while BL32 corresponds to the secure image type. A NULL pointer is returned 45 * if the image does not exist. 46 ******************************************************************************/ 47 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 48 { 49 entry_point_info_t *next_image_info; 50 51 assert(sec_state_is_valid(type)); 52 next_image_info = (type == NON_SECURE) 53 ? &bl33_image_ep_info : &bl32_image_ep_info; 54 /* 55 * None of the images on the ARM development platforms can have 0x0 56 * as the entrypoint 57 */ 58 if (next_image_info->pc) 59 return next_image_info; 60 else 61 return NULL; 62 } 63 64 /******************************************************************************* 65 * Perform any BL31 early platform setup common to ARM standard platforms. 66 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 67 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 68 * done before the MMU is initialized so that the memory layout can be used 69 * while creating page tables. BL2 has flushed this information to memory, so 70 * we are guaranteed to pick up good data. 71 ******************************************************************************/ 72 #if LOAD_IMAGE_V2 73 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 74 uintptr_t hw_config, void *plat_params_from_bl2) 75 #else 76 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, 77 uintptr_t hw_config, void *plat_params_from_bl2) 78 #endif 79 { 80 /* Initialize the console to provide early debug support */ 81 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 82 ARM_CONSOLE_BAUDRATE); 83 84 #if RESET_TO_BL31 85 /* There are no parameters from BL2 if BL31 is a reset vector */ 86 assert(from_bl2 == NULL); 87 assert(plat_params_from_bl2 == NULL); 88 89 # ifdef BL32_BASE 90 /* Populate entry point information for BL32 */ 91 SET_PARAM_HEAD(&bl32_image_ep_info, 92 PARAM_EP, 93 VERSION_1, 94 0); 95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 96 bl32_image_ep_info.pc = BL32_BASE; 97 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 98 # endif /* BL32_BASE */ 99 100 /* Populate entry point information for BL33 */ 101 SET_PARAM_HEAD(&bl33_image_ep_info, 102 PARAM_EP, 103 VERSION_1, 104 0); 105 /* 106 * Tell BL31 where the non-trusted software image 107 * is located and the entry state information 108 */ 109 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 110 111 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 112 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 113 114 # if ARM_LINUX_KERNEL_AS_BL33 115 /* 116 * According to the file ``Documentation/arm64/booting.txt`` of the 117 * Linux kernel tree, Linux expects the physical address of the device 118 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 119 * must be 0. 120 */ 121 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 122 bl33_image_ep_info.args.arg1 = 0U; 123 bl33_image_ep_info.args.arg2 = 0U; 124 bl33_image_ep_info.args.arg3 = 0U; 125 # endif 126 127 #else /* RESET_TO_BL31 */ 128 129 /* 130 * In debug builds, we pass a special value in 'plat_params_from_bl2' 131 * to verify platform parameters from BL2 to BL31. 132 * In release builds, it's not used. 133 */ 134 assert(((unsigned long long)plat_params_from_bl2) == 135 ARM_BL31_PLAT_PARAM_VAL); 136 137 # if LOAD_IMAGE_V2 138 /* 139 * Check params passed from BL2 should not be NULL, 140 */ 141 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 142 assert(params_from_bl2 != NULL); 143 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 144 assert(params_from_bl2->h.version >= VERSION_2); 145 146 bl_params_node_t *bl_params = params_from_bl2->head; 147 148 /* 149 * Copy BL33 and BL32 (if present), entry point information. 150 * They are stored in Secure RAM, in BL2's address space. 151 */ 152 while (bl_params) { 153 if (bl_params->image_id == BL32_IMAGE_ID) 154 bl32_image_ep_info = *bl_params->ep_info; 155 156 if (bl_params->image_id == BL33_IMAGE_ID) 157 bl33_image_ep_info = *bl_params->ep_info; 158 159 bl_params = bl_params->next_params_info; 160 } 161 162 if (bl33_image_ep_info.pc == 0) 163 panic(); 164 165 # else /* LOAD_IMAGE_V2 */ 166 167 /* 168 * Check params passed from BL2 should not be NULL, 169 */ 170 assert(from_bl2 != NULL); 171 assert(from_bl2->h.type == PARAM_BL31); 172 assert(from_bl2->h.version >= VERSION_1); 173 174 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ 175 assert(soc_fw_config == 0); 176 assert(hw_config == 0); 177 178 /* 179 * Copy BL32 (if populated by BL2) and BL33 entry point information. 180 * They are stored in Secure RAM, in BL2's address space. 181 */ 182 if (from_bl2->bl32_ep_info) 183 bl32_image_ep_info = *from_bl2->bl32_ep_info; 184 bl33_image_ep_info = *from_bl2->bl33_ep_info; 185 186 # endif /* LOAD_IMAGE_V2 */ 187 #endif /* RESET_TO_BL31 */ 188 } 189 190 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 191 u_register_t arg2, u_register_t arg3) 192 { 193 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 194 195 /* 196 * Initialize Interconnect for this cluster during cold boot. 197 * No need for locks as no other CPU is active. 198 */ 199 plat_arm_interconnect_init(); 200 201 /* 202 * Enable Interconnect coherency for the primary CPU's cluster. 203 * Earlier bootloader stages might already do this (e.g. Trusted 204 * Firmware's BL1 does it) but we can't assume so. There is no harm in 205 * executing this code twice anyway. 206 * Platform specific PSCI code will enable coherency for other 207 * clusters. 208 */ 209 plat_arm_interconnect_enter_coherency(); 210 } 211 212 /******************************************************************************* 213 * Perform any BL31 platform setup common to ARM standard platforms 214 ******************************************************************************/ 215 void arm_bl31_platform_setup(void) 216 { 217 /* Initialize the GIC driver, cpu and distributor interfaces */ 218 plat_arm_gic_driver_init(); 219 plat_arm_gic_init(); 220 221 #if RESET_TO_BL31 222 /* 223 * Do initial security configuration to allow DRAM/device access 224 * (if earlier BL has not already done so). 225 */ 226 plat_arm_security_setup(); 227 228 #if defined(PLAT_ARM_MEM_PROT_ADDR) 229 arm_nor_psci_do_dyn_mem_protect(); 230 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 231 232 #endif /* RESET_TO_BL31 */ 233 234 /* Enable and initialize the System level generic timer */ 235 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 236 CNTCR_FCREQ(0) | CNTCR_EN); 237 238 /* Allow access to the System counter timer module */ 239 arm_configure_sys_timer(); 240 241 /* Initialize power controller before setting up topology */ 242 plat_arm_pwrc_setup(); 243 244 #if RAS_EXTENSION 245 ras_init(); 246 #endif 247 } 248 249 /******************************************************************************* 250 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 251 * standard platforms 252 ******************************************************************************/ 253 void arm_bl31_plat_runtime_setup(void) 254 { 255 /* Initialize the runtime console */ 256 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 257 ARM_CONSOLE_BAUDRATE); 258 } 259 260 void bl31_platform_setup(void) 261 { 262 arm_bl31_platform_setup(); 263 } 264 265 void bl31_plat_runtime_setup(void) 266 { 267 arm_bl31_plat_runtime_setup(); 268 } 269 270 /******************************************************************************* 271 * Perform the very early platform specific architectural setup shared between 272 * ARM standard platforms. This only does basic initialization. Later 273 * architectural setup (bl31_arch_setup()) does not do anything platform 274 * specific. 275 ******************************************************************************/ 276 void arm_bl31_plat_arch_setup(void) 277 { 278 arm_setup_page_tables(BL31_BASE, 279 BL31_END - BL31_BASE, 280 BL_CODE_BASE, 281 BL_CODE_END, 282 BL_RO_DATA_BASE, 283 BL_RO_DATA_END 284 #if USE_COHERENT_MEM 285 , BL_COHERENT_RAM_BASE, 286 BL_COHERENT_RAM_END 287 #endif 288 ); 289 enable_mmu_el3(0); 290 } 291 292 void bl31_plat_arch_setup(void) 293 { 294 arm_bl31_plat_arch_setup(); 295 } 296