1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <bl_common.h> 8 #include <common_def.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <generic_delay_timer.h> 12 #include <mcucfg.h> 13 #include <mmio.h> 14 #include <mtcmos.h> 15 #include <plat_arm.h> 16 #include <plat_private.h> 17 #include <platform.h> 18 #include <spm.h> 19 20 static entry_point_info_t bl32_ep_info; 21 static entry_point_info_t bl33_ep_info; 22 23 static void platform_setup_cpu(void) 24 { 25 /* turn off all the little core's power except cpu 0 */ 26 mtcmos_little_cpu_off(); 27 28 /* setup big cores */ 29 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 30 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 31 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 32 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 33 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 34 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 35 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 36 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 37 MP1_SW_CG_GEN); 38 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 39 MP1_L2RSTDISABLE); 40 41 /* set big cores arm64 boot mode */ 42 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 43 MP1_CPUCFG_64BIT); 44 45 /* set LITTLE cores arm64 boot mode */ 46 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 47 MP0_CPUCFG_64BIT); 48 49 /* enable dcm control */ 50 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 51 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 52 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 53 INFRACLK_PSYS_DYNAMIC_CG_EN); 54 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 55 L2C_SRAM_DCM_EN); 56 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 57 MCU_BUS_DCM_EN); 58 } 59 60 static void platform_setup_sram(void) 61 { 62 /* protect BL31 memory from non-secure read/write access */ 63 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 64 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 65 } 66 67 /******************************************************************************* 68 * Return a pointer to the 'entry_point_info' structure of the next image for 69 * the security state specified. BL33 corresponds to the non-secure image type 70 * while BL32 corresponds to the secure image type. A NULL pointer is returned 71 * if the image does not exist. 72 ******************************************************************************/ 73 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 74 { 75 entry_point_info_t *next_image_info; 76 77 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 78 79 /* None of the images on this platform can have 0x0 as the entrypoint */ 80 if (next_image_info->pc) 81 return next_image_info; 82 else 83 return NULL; 84 } 85 86 /******************************************************************************* 87 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 88 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 89 * are lost (potentially). This needs to be done before the MMU is initialized 90 * so that the memory layout can be used while creating page tables. 91 * BL2 has flushed this information to memory, so we are guaranteed to pick up 92 * good data. 93 ******************************************************************************/ 94 void bl31_early_platform_setup(bl31_params_t *from_bl2, 95 void *plat_params_from_bl2) 96 { 97 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 98 99 VERBOSE("bl31_setup\n"); 100 101 assert(from_bl2 != NULL); 102 assert(from_bl2->h.type == PARAM_BL31); 103 assert(from_bl2->h.version >= VERSION_1); 104 105 bl32_ep_info = *from_bl2->bl32_ep_info; 106 bl33_ep_info = *from_bl2->bl33_ep_info; 107 } 108 109 /******************************************************************************* 110 * Perform any BL3-1 platform setup code 111 ******************************************************************************/ 112 void bl31_platform_setup(void) 113 { 114 platform_setup_cpu(); 115 platform_setup_sram(); 116 117 generic_delay_timer_init(); 118 119 /* Initialize the gic cpu and distributor interfaces */ 120 plat_arm_gic_driver_init(); 121 plat_arm_gic_init(); 122 123 #if ENABLE_PLAT_COMPAT 124 /* Topologies are best known to the platform. */ 125 mt_setup_topology(); 126 #endif 127 128 /* Initialize spm at boot time */ 129 spm_boot_init(); 130 } 131 132 /******************************************************************************* 133 * Perform the very early platform specific architectural setup here. At the 134 * moment this is only intializes the mmu in a quick and dirty way. 135 ******************************************************************************/ 136 void bl31_plat_arch_setup(void) 137 { 138 plat_cci_init(); 139 plat_cci_enable(); 140 141 plat_configure_mmu_el3(BL_CODE_BASE, 142 BL_COHERENT_RAM_END - BL_CODE_BASE, 143 BL_CODE_BASE, 144 BL_CODE_END, 145 BL_COHERENT_RAM_BASE, 146 BL_COHERENT_RAM_END); 147 } 148 149