1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <sys/types.h> 14 #include <utils.h> 15 #include <utils_def.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 /* 20 * Returns 1 if the provided granule size is supported, 0 otherwise. 21 */ 22 int xlat_arch_is_granule_size_supported(size_t size) 23 { 24 u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); 25 26 if (size == (4U * 1024U)) { 27 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & 28 ID_AA64MMFR0_EL1_TGRAN4_MASK) == 29 ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; 30 } else if (size == (16U * 1024U)) { 31 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & 32 ID_AA64MMFR0_EL1_TGRAN16_MASK) == 33 ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; 34 } else if (size == (64U * 1024U)) { 35 return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & 36 ID_AA64MMFR0_EL1_TGRAN64_MASK) == 37 ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; 38 } 39 40 return 0; 41 } 42 43 size_t xlat_arch_get_max_supported_granule_size(void) 44 { 45 if (xlat_arch_is_granule_size_supported(64U * 1024U)) { 46 return 64U * 1024U; 47 } else if (xlat_arch_is_granule_size_supported(16U * 1024U)) { 48 return 16U * 1024U; 49 } else { 50 assert(xlat_arch_is_granule_size_supported(4U * 1024U)); 51 return 4U * 1024U; 52 } 53 } 54 55 unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) 56 { 57 /* Physical address can't exceed 48 bits */ 58 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 59 60 /* 48 bits address */ 61 if (max_addr & ADDR_MASK_44_TO_47) 62 return TCR_PS_BITS_256TB; 63 64 /* 44 bits address */ 65 if (max_addr & ADDR_MASK_42_TO_43) 66 return TCR_PS_BITS_16TB; 67 68 /* 42 bits address */ 69 if (max_addr & ADDR_MASK_40_TO_41) 70 return TCR_PS_BITS_4TB; 71 72 /* 40 bits address */ 73 if (max_addr & ADDR_MASK_36_TO_39) 74 return TCR_PS_BITS_1TB; 75 76 /* 36 bits address */ 77 if (max_addr & ADDR_MASK_32_TO_35) 78 return TCR_PS_BITS_64GB; 79 80 return TCR_PS_BITS_4GB; 81 } 82 83 #if ENABLE_ASSERTIONS 84 /* 85 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is 86 * supported in ARMv8.2 onwards. 87 */ 88 static const unsigned int pa_range_bits_arr[] = { 89 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 90 PARANGE_0101, PARANGE_0110 91 }; 92 93 unsigned long long xlat_arch_get_max_supported_pa(void) 94 { 95 u_register_t pa_range = read_id_aa64mmfr0_el1() & 96 ID_AA64MMFR0_EL1_PARANGE_MASK; 97 98 /* All other values are reserved */ 99 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 100 101 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; 102 } 103 #endif /* ENABLE_ASSERTIONS*/ 104 105 int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) 106 { 107 if (ctx->xlat_regime == EL1_EL0_REGIME) { 108 assert(xlat_arch_current_el() >= 1); 109 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 110 } else { 111 assert(ctx->xlat_regime == EL3_REGIME); 112 assert(xlat_arch_current_el() >= 3); 113 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 114 } 115 } 116 117 118 void xlat_arch_tlbi_va(uintptr_t va) 119 { 120 #if IMAGE_EL == 1 121 assert(IS_IN_EL(1)); 122 xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); 123 #elif IMAGE_EL == 3 124 assert(IS_IN_EL(3)); 125 xlat_arch_tlbi_va_regime(va, EL3_REGIME); 126 #endif 127 } 128 129 void xlat_arch_tlbi_va_regime(uintptr_t va, xlat_regime_t xlat_regime) 130 { 131 /* 132 * Ensure the translation table write has drained into memory before 133 * invalidating the TLB entry. 134 */ 135 dsbishst(); 136 137 /* 138 * This function only supports invalidation of TLB entries for the EL3 139 * and EL1&0 translation regimes. 140 * 141 * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher 142 * exception level (see section D4.9.2 of the ARM ARM rev B.a). 143 */ 144 if (xlat_regime == EL1_EL0_REGIME) { 145 assert(xlat_arch_current_el() >= 1); 146 tlbivaae1is(TLBI_ADDR(va)); 147 } else { 148 assert(xlat_regime == EL3_REGIME); 149 assert(xlat_arch_current_el() >= 3); 150 tlbivae3is(TLBI_ADDR(va)); 151 } 152 } 153 154 void xlat_arch_tlbi_va_sync(void) 155 { 156 /* 157 * A TLB maintenance instruction can complete at any time after 158 * it is issued, but is only guaranteed to be complete after the 159 * execution of DSB by the PE that executed the TLB maintenance 160 * instruction. After the TLB invalidate instruction is 161 * complete, no new memory accesses using the invalidated TLB 162 * entries will be observed by any observer of the system 163 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 164 * "Ordering and completion of TLB maintenance instructions". 165 */ 166 dsbish(); 167 168 /* 169 * The effects of a completed TLB maintenance instruction are 170 * only guaranteed to be visible on the PE that executed the 171 * instruction after the execution of an ISB instruction by the 172 * PE that executed the TLB maintenance instruction. 173 */ 174 isb(); 175 } 176 177 int xlat_arch_current_el(void) 178 { 179 int el = GET_EL(read_CurrentEl()); 180 181 assert(el > 0); 182 183 return el; 184 } 185 186 /******************************************************************************* 187 * Macro generating the code for the function enabling the MMU in the given 188 * exception level, assuming that the pagetables have already been created. 189 * 190 * _el: Exception level at which the function will run 191 * _tlbi_fct: Function to invalidate the TLBs at the current 192 * exception level 193 ******************************************************************************/ 194 #define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \ 195 static void enable_mmu_internal_el##_el(int flags, \ 196 uint64_t mair, \ 197 uint64_t tcr, \ 198 uint64_t ttbr) \ 199 { \ 200 uint32_t sctlr = read_sctlr_el##_el(); \ 201 assert((sctlr & SCTLR_M_BIT) == 0); \ 202 \ 203 /* Invalidate TLBs at the current exception level */ \ 204 _tlbi_fct(); \ 205 \ 206 write_mair_el##_el(mair); \ 207 write_tcr_el##_el(tcr); \ 208 \ 209 /* Set TTBR bits as well */ \ 210 if (ARM_ARCH_AT_LEAST(8, 2)) { \ 211 /* Enable CnP bit so as to share page tables */ \ 212 /* with all PEs. This is mandatory for */ \ 213 /* ARMv8.2 implementations. */ \ 214 ttbr |= TTBR_CNP_BIT; \ 215 } \ 216 write_ttbr0_el##_el(ttbr); \ 217 \ 218 /* Ensure all translation table writes have drained */ \ 219 /* into memory, the TLB invalidation is complete, */ \ 220 /* and translation register writes are committed */ \ 221 /* before enabling the MMU */ \ 222 dsbish(); \ 223 isb(); \ 224 \ 225 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 226 if (flags & DISABLE_DCACHE) \ 227 sctlr &= ~SCTLR_C_BIT; \ 228 else \ 229 sctlr |= SCTLR_C_BIT; \ 230 \ 231 write_sctlr_el##_el(sctlr); \ 232 \ 233 /* Ensure the MMU enable takes effect immediately */ \ 234 isb(); \ 235 } 236 237 /* Define EL1 and EL3 variants of the function enabling the MMU */ 238 #if IMAGE_EL == 1 239 DEFINE_ENABLE_MMU_EL(1, tlbivmalle1) 240 #elif IMAGE_EL == 3 241 DEFINE_ENABLE_MMU_EL(3, tlbialle3) 242 #endif 243 244 void enable_mmu_arch(unsigned int flags, 245 uint64_t *base_table, 246 unsigned long long max_pa, 247 uintptr_t max_va) 248 { 249 uint64_t mair, ttbr, tcr; 250 251 /* Set attributes in the right indices of the MAIR. */ 252 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 253 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); 254 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); 255 256 ttbr = (uint64_t) base_table; 257 258 /* 259 * Set TCR bits as well. 260 */ 261 262 /* 263 * Limit the input address ranges and memory region sizes translated 264 * using TTBR0 to the given virtual address space size. 265 */ 266 assert(max_va < UINTPTR_MAX); 267 uintptr_t virtual_addr_space_size = max_va + 1; 268 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 269 /* 270 * __builtin_ctzll(0) is undefined but here we are guaranteed that 271 * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. 272 */ 273 tcr = 64 - __builtin_ctzll(virtual_addr_space_size); 274 275 /* 276 * Set the cacheability and shareability attributes for memory 277 * associated with translation table walks. 278 */ 279 if (flags & XLAT_TABLE_NC) { 280 /* Inner & outer non-cacheable non-shareable. */ 281 tcr |= TCR_SH_NON_SHAREABLE | 282 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; 283 } else { 284 /* Inner & outer WBWA & shareable. */ 285 tcr |= TCR_SH_INNER_SHAREABLE | 286 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; 287 } 288 289 /* 290 * It is safer to restrict the max physical address accessible by the 291 * hardware as much as possible. 292 */ 293 unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); 294 295 #if IMAGE_EL == 1 296 assert(IS_IN_EL(1)); 297 /* 298 * TCR_EL1.EPD1: Disable translation table walk for addresses that are 299 * translated using TTBR1_EL1. 300 */ 301 tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); 302 enable_mmu_internal_el1(flags, mair, tcr, ttbr); 303 #elif IMAGE_EL == 3 304 assert(IS_IN_EL(3)); 305 tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); 306 enable_mmu_internal_el3(flags, mair, tcr, ttbr); 307 #endif 308 } 309