1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CSS_DEF_H__ 8 #define __CSS_DEF_H__ 9 10 #include <arm_def.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <tzc400.h> 14 15 /************************************************************************* 16 * Definitions common to all ARM Compute SubSystems (CSS) 17 *************************************************************************/ 18 #define NSROM_BASE 0x1f000000 19 #define NSROM_SIZE 0x00001000 20 21 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 22 #define CSS_DEVICE_BASE 0x20000000 23 #define CSS_DEVICE_SIZE 0x0e000000 24 25 /* System Security Control Registers */ 26 #define SSC_REG_BASE 0x2a420000 27 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 28 29 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 30 #define CSS_NIC400_SLAVE_BOOTSECURE 8 31 32 /* Interrupt handling constants */ 33 #define CSS_IRQ_MHU 69 34 #define CSS_IRQ_GPU_SMMU_0 71 35 #define CSS_IRQ_TZC 80 36 #define CSS_IRQ_TZ_WDOG 86 37 #define CSS_IRQ_SEC_SYS_TIMER 91 38 39 /* MHU register offsets */ 40 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 41 42 /* 43 * Define a list of Group 1 Secure interrupt properties as per GICv3 44 * terminology. On a GICv2 system or mode, the interrupts will be treated as 45 * Group 0 interrupts. 46 */ 47 #define CSS_G1S_IRQ_PROPS(grp) \ 48 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 49 GIC_INTR_CFG_LEVEL), \ 50 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 51 GIC_INTR_CFG_LEVEL), \ 52 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 53 GIC_INTR_CFG_LEVEL), \ 54 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 55 GIC_INTR_CFG_LEVEL), \ 56 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 57 GIC_INTR_CFG_LEVEL) 58 59 #if CSS_USE_SCMI_SDS_DRIVER 60 /* Memory region for shared data storage */ 61 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 62 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 63 /* 64 * The SCMI Channel is placed right after the SDS region 65 */ 66 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 67 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 68 69 /* Trusted mailbox base address common to all CSS */ 70 /* If SDS is present, then mailbox is at top of SRAM */ 71 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 72 73 /* Number of retries for SCP_RAM_READY flag */ 74 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 75 76 #else 77 /* 78 * SCP <=> AP boot configuration 79 * 80 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 81 * the start of the Trusted SRAM. 82 * 83 * Note that the value stored at this address is only valid at boot time, before 84 * the SCP_BL2 image is transferred to SCP. 85 */ 86 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 87 88 /* Trusted mailbox base address common to all CSS */ 89 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 90 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 91 92 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 93 94 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 95 CSS_DEVICE_BASE, \ 96 CSS_DEVICE_SIZE, \ 97 MT_DEVICE | MT_RW | MT_SECURE) 98 99 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 100 NSRAM_BASE, \ 101 NSRAM_SIZE, \ 102 MT_DEVICE | MT_RW | MT_NS) 103 104 /* Platform ID address */ 105 #define SSC_VERSION_OFFSET 0x040 106 107 #define SSC_VERSION_CONFIG_SHIFT 28 108 #define SSC_VERSION_MAJOR_REV_SHIFT 24 109 #define SSC_VERSION_MINOR_REV_SHIFT 20 110 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 111 #define SSC_VERSION_PART_NUM_SHIFT 0x0 112 #define SSC_VERSION_CONFIG_MASK 0xf 113 #define SSC_VERSION_MAJOR_REV_MASK 0xf 114 #define SSC_VERSION_MINOR_REV_MASK 0xf 115 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 116 #define SSC_VERSION_PART_NUM_MASK 0xfff 117 118 /* SSC debug configuration registers */ 119 #define SSC_DBGCFG_SET 0x14 120 #define SSC_DBGCFG_CLR 0x18 121 122 #define SPIDEN_INT_CLR_SHIFT 6 123 #define SPIDEN_SEL_SET_SHIFT 7 124 125 #ifndef __ASSEMBLY__ 126 127 /* SSC_VERSION related accessors */ 128 129 /* Returns the part number of the platform */ 130 #define GET_SSC_VERSION_PART_NUM(val) \ 131 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 132 SSC_VERSION_PART_NUM_MASK) 133 134 /* Returns the configuration number of the platform */ 135 #define GET_SSC_VERSION_CONFIG(val) \ 136 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 137 SSC_VERSION_CONFIG_MASK) 138 139 #endif /* __ASSEMBLY__ */ 140 141 /************************************************************************* 142 * Required platform porting definitions common to all 143 * ARM Compute SubSystems (CSS) 144 ************************************************************************/ 145 146 /* 147 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 148 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 149 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 150 * an SCP_BL2/SCP_BL2U image. 151 */ 152 #if CSS_LOAD_SCP_IMAGES 153 154 #if ARM_BL31_IN_DRAM 155 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 156 #endif 157 158 /* 159 * Load address of SCP_BL2 in CSS platform ports 160 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 161 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 162 * BL31 is loaded over the top. 163 */ 164 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 165 #define SCP_BL2_LIMIT BL2_BASE 166 167 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 168 #define SCP_BL2U_LIMIT BL2_BASE 169 #endif /* CSS_LOAD_SCP_IMAGES */ 170 171 /* Load address of Non-Secure Image for CSS platform ports */ 172 #define PLAT_ARM_NS_IMAGE_OFFSET U(0xE0000000) 173 174 /* TZC related constants */ 175 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 176 177 /* 178 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 179 * command 180 */ 181 #define CSS_CLUSTER_PWR_STATE_ON 0 182 #define CSS_CLUSTER_PWR_STATE_OFF 3 183 184 #define CSS_CPU_PWR_STATE_ON 1 185 #define CSS_CPU_PWR_STATE_OFF 0 186 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 187 188 #endif /* __CSS_DEF_H__ */ 189