1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <gicv2.h> 12 #include <hi6220.h> 13 #include <hikey_def.h> 14 #include <hisi_ipc.h> 15 #include <hisi_pwrc.h> 16 #include <hisi_sram_map.h> 17 #include <mmio.h> 18 #include <psci.h> 19 #include <sp804_delay_timer.h> 20 21 #define CORE_PWR_STATE(state) \ 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 23 #define CLUSTER_PWR_STATE(state) \ 24 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 25 #define SYSTEM_PWR_STATE(state) \ 26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 27 28 static uintptr_t hikey_sec_entrypoint; 29 30 static int hikey_pwr_domain_on(u_register_t mpidr) 31 { 32 int cpu, cluster; 33 int curr_cluster; 34 35 cluster = MPIDR_AFFLVL1_VAL(mpidr); 36 cpu = MPIDR_AFFLVL0_VAL(mpidr); 37 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); 38 if (cluster != curr_cluster) 39 hisi_ipc_cluster_on(cpu, cluster); 40 41 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 42 hisi_pwrc_enable_debug(cpu, cluster); 43 hisi_ipc_cpu_on(cpu, cluster); 44 45 return 0; 46 } 47 48 static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) 49 { 50 unsigned long mpidr; 51 int cpu, cluster; 52 53 mpidr = read_mpidr(); 54 cluster = MPIDR_AFFLVL1_VAL(mpidr); 55 cpu = MPIDR_AFFLVL0_VAL(mpidr); 56 57 58 /* 59 * Enable CCI coherency for this cluster. 60 * No need for locks as no other cpu is active at the moment. 61 */ 62 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 63 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 64 65 /* Zero the jump address in the mailbox for this cpu */ 66 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 67 68 /* Program the GIC per-cpu distributor or re-distributor interface */ 69 gicv2_pcpu_distif_init(); 70 /* Enable the GIC cpu interface */ 71 gicv2_cpuif_enable(); 72 } 73 74 void hikey_pwr_domain_off(const psci_power_state_t *target_state) 75 { 76 unsigned long mpidr; 77 int cpu, cluster; 78 79 mpidr = read_mpidr(); 80 cluster = MPIDR_AFFLVL1_VAL(mpidr); 81 cpu = MPIDR_AFFLVL0_VAL(mpidr); 82 83 gicv2_cpuif_disable(); 84 hisi_ipc_cpu_off(cpu, cluster); 85 86 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 87 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 89 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 90 91 hisi_ipc_cluster_off(cpu, cluster); 92 } 93 } 94 95 static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state) 96 { 97 u_register_t mpidr = read_mpidr_el1(); 98 unsigned int cpu = mpidr & MPIDR_CPU_MASK; 99 unsigned int cluster = 100 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; 101 102 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 103 return; 104 105 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 106 107 /* Program the jump address for the target cpu */ 108 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 109 110 gicv2_cpuif_disable(); 111 112 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 113 hisi_ipc_cpu_suspend(cpu, cluster); 114 } 115 116 /* Perform the common cluster specific operations */ 117 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 118 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 119 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 120 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 121 122 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 123 hisi_pwrc_set_cluster_wfi(1); 124 hisi_pwrc_set_cluster_wfi(0); 125 hisi_ipc_psci_system_off(); 126 } else 127 hisi_ipc_cluster_suspend(cpu, cluster); 128 } 129 } 130 131 static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 132 { 133 unsigned long mpidr; 134 unsigned int cluster, cpu; 135 136 /* Nothing to be done on waking up from retention from CPU level */ 137 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 138 return; 139 140 /* Get the mpidr for this cpu */ 141 mpidr = read_mpidr_el1(); 142 cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT; 143 cpu = mpidr & MPIDR_CPU_MASK; 144 145 /* Enable CCI coherency for cluster */ 146 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 147 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 148 149 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 150 151 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 152 gicv2_distif_init(); 153 gicv2_pcpu_distif_init(); 154 gicv2_cpuif_enable(); 155 } else { 156 gicv2_pcpu_distif_init(); 157 gicv2_cpuif_enable(); 158 } 159 } 160 161 static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state) 162 { 163 int i; 164 165 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 166 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 167 } 168 169 static void __dead2 hikey_system_off(void) 170 { 171 NOTICE("%s: off system\n", __func__); 172 173 /* Pull down GPIO_0_0 to trigger PMIC shutdown */ 174 mmio_write_32(0xF8001810, 0x2); /* Pinmux */ 175 mmio_write_8(0xF8011400, 1); /* Pin direction */ 176 mmio_write_8(0xF8011004, 0); /* Pin output value */ 177 178 /* Wait for 2s to power off system by PMIC */ 179 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 180 mdelay(2000); 181 182 /* 183 * PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low, 184 * and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2 185 * through Jumper 1-2. So, to complete shutdown, user needs to manually 186 * remove Jumper 1-2. 187 */ 188 NOTICE("+------------------------------------------+\n"); 189 NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n"); 190 NOTICE("| DANGER: SoC is still burning. DANGER! |\n"); 191 NOTICE("| Board will be reboot to avoid overheat |\n"); 192 NOTICE("+------------------------------------------+\n"); 193 194 /* Send the system reset request */ 195 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 196 197 wfi(); 198 panic(); 199 } 200 201 static void __dead2 hikey_system_reset(void) 202 { 203 /* Send the system reset request */ 204 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 205 isb(); 206 dsb(); 207 208 wfi(); 209 panic(); 210 } 211 212 int hikey_validate_power_state(unsigned int power_state, 213 psci_power_state_t *req_state) 214 { 215 int pstate = psci_get_pstate_type(power_state); 216 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 217 int i; 218 219 assert(req_state); 220 221 if (pwr_lvl > PLAT_MAX_PWR_LVL) 222 return PSCI_E_INVALID_PARAMS; 223 224 /* Sanity check the requested state */ 225 if (pstate == PSTATE_TYPE_STANDBY) { 226 /* 227 * It's possible to enter standby only on power level 0 228 * Ignore any other power level. 229 */ 230 if (pwr_lvl != MPIDR_AFFLVL0) 231 return PSCI_E_INVALID_PARAMS; 232 233 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 234 PLAT_MAX_RET_STATE; 235 } else { 236 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) 237 req_state->pwr_domain_state[i] = 238 PLAT_MAX_OFF_STATE; 239 } 240 241 /* 242 * We expect the 'state id' to be zero. 243 */ 244 if (psci_get_pstate_id(power_state)) 245 return PSCI_E_INVALID_PARAMS; 246 247 return PSCI_E_SUCCESS; 248 } 249 250 static int hikey_validate_ns_entrypoint(uintptr_t entrypoint) 251 { 252 /* 253 * Check if the non secure entrypoint lies within the non 254 * secure DRAM. 255 */ 256 if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) 257 return PSCI_E_SUCCESS; 258 259 return PSCI_E_INVALID_ADDRESS; 260 } 261 262 static const plat_psci_ops_t hikey_psci_ops = { 263 .cpu_standby = NULL, 264 .pwr_domain_on = hikey_pwr_domain_on, 265 .pwr_domain_on_finish = hikey_pwr_domain_on_finish, 266 .pwr_domain_off = hikey_pwr_domain_off, 267 .pwr_domain_suspend = hikey_pwr_domain_suspend, 268 .pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish, 269 .system_off = hikey_system_off, 270 .system_reset = hikey_system_reset, 271 .validate_power_state = hikey_validate_power_state, 272 .validate_ns_entrypoint = hikey_validate_ns_entrypoint, 273 .get_sys_suspend_power_state = hikey_get_sys_suspend_power_state, 274 }; 275 276 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 277 const plat_psci_ops_t **psci_ops) 278 { 279 hikey_sec_entrypoint = sec_entrypoint; 280 281 /* 282 * Initialize PSCI ops struct 283 */ 284 *psci_ops = &hikey_psci_ops; 285 return 0; 286 } 287