1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey960_def.h" 12 13 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 14 #define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 15 16 /* 17 * Generic platform constants 18 */ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE 0x800 22 23 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 24 25 #define PLATFORM_CACHE_LINE_SIZE 64 26 #define PLATFORM_CLUSTER_COUNT 2 27 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_CORE_COUNT_PER_CLUSTER) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 31 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 32 PLATFORM_CLUSTER_COUNT + 1) 33 34 #define PLAT_MAX_RET_STATE 1 35 #define PLAT_MAX_OFF_STATE 2 36 37 #define MAX_IO_DEVICES 3 38 #define MAX_IO_HANDLES 4 39 /* UFS RPMB and UFS User Data */ 40 #define MAX_IO_BLOCK_DEVICES 2 41 42 43 /* 44 * Platform memory map related constants 45 */ 46 47 /* 48 * BL1 specific defines. 49 */ 50 #define BL1_RO_BASE (0x1AC00000) 51 #define BL1_RO_LIMIT (BL1_RO_BASE + 0x10000) 52 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC1_0000 */ 53 #define BL1_RW_SIZE (0x00188000) 54 #define BL1_RW_LIMIT (0x1B000000) 55 56 /* 57 * BL2 specific defines. 58 */ 59 #define BL2_BASE (0x1AC00000) 60 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */ 61 62 /* 63 * BL31 specific defines. 64 */ 65 #define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */ 66 #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ 67 68 /* 69 * BL3-2 specific defines. 70 */ 71 72 /* 73 * The TSP currently executes from TZC secured area of DRAM. 74 */ 75 #define BL32_DRAM_BASE DDR_SEC_BASE 76 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 77 78 #ifdef SPD_opteed 79 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 80 #define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 81 #define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 82 #endif 83 84 #if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID) 85 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 86 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 87 #define BL32_BASE BL32_DRAM_BASE 88 #define BL32_LIMIT BL32_DRAM_LIMIT 89 #elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID) 90 #error "SRAM storage of TSP payload is currently unsupported" 91 #else 92 #error "Currently unsupported HIKEY960_TSP_LOCATION_ID value" 93 #endif 94 95 /* BL32 is mandatory in AArch32 */ 96 #ifndef AARCH32 97 #ifdef SPD_none 98 #undef BL32_BASE 99 #endif /* SPD_none */ 100 #endif 101 102 #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */ 103 #define NS_BL1U_SIZE (0x00100000) 104 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 105 106 #define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */ 107 #define HIKEY960_NS_TMP_OFFSET (0x1AE00000) 108 109 #define SCP_BL2_BASE (0x89C80000) 110 #define SCP_BL2_SIZE (0x00040000) 111 112 /* 113 * Platform specific page table and MMU setup constants 114 */ 115 #define ADDR_SPACE_SIZE (1ULL << 32) 116 117 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32) 118 #define MAX_XLAT_TABLES 3 119 #endif 120 121 #ifdef IMAGE_BL2 122 #ifdef SPD_opteed 123 #define MAX_XLAT_TABLES 4 124 #else 125 #define MAX_XLAT_TABLES 3 126 #endif 127 #endif 128 129 #define MAX_MMAP_REGIONS 16 130 131 /* 132 * Declarations and constants to access the mailboxes safely. Each mailbox is 133 * aligned on the biggest cache line size in the platform. This is known only 134 * to the platform as it might have a combination of integrated and external 135 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 136 * line at any cache level. They could belong to different cpus/clusters & 137 * get written while being protected by different locks causing corruption of 138 * a valid mailbox address. 139 */ 140 #define CACHE_WRITEBACK_SHIFT 6 141 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 142 143 #endif /* __PLATFORM_DEF_H__ */ 144