1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_H__ 8 #define __GICV3_H__ 9 10 /******************************************************************************* 11 * GICv3 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt group definitions */ 14 #define INTR_GROUP1S 0 15 #define INTR_GROUP0 1 16 #define INTR_GROUP1NS 2 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1S_INTID 1020 20 #define PENDING_G1NS_INTID 1021 21 22 /* Constant to categorize LPI interrupt */ 23 #define MIN_LPI_ID 8192 24 25 /* GICv3 can only target up to 16 PEs with SGI */ 26 #define GICV3_MAX_SGI_TARGETS 16 27 28 /******************************************************************************* 29 * GICv3 specific Distributor interface register offsets and constants. 30 ******************************************************************************/ 31 #define GICD_STATUSR 0x10 32 #define GICD_SETSPI_NSR 0x40 33 #define GICD_CLRSPI_NSR 0x48 34 #define GICD_SETSPI_SR 0x50 35 #define GICD_CLRSPI_SR 0x50 36 #define GICD_IGRPMODR 0xd00 37 /* 38 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and 39 * n >= 32, making the effective offset as 0x6100. 40 */ 41 #define GICD_IROUTER 0x6000 42 #define GICD_PIDR2_GICV3 0xffe8 43 44 #define IGRPMODR_SHIFT 5 45 46 /* GICD_CTLR bit definitions */ 47 #define CTLR_ENABLE_G1NS_SHIFT 1 48 #define CTLR_ENABLE_G1S_SHIFT 2 49 #define CTLR_ARE_S_SHIFT 4 50 #define CTLR_ARE_NS_SHIFT 5 51 #define CTLR_DS_SHIFT 6 52 #define CTLR_E1NWF_SHIFT 7 53 #define GICD_CTLR_RWP_SHIFT 31 54 55 #define CTLR_ENABLE_G1NS_MASK 0x1 56 #define CTLR_ENABLE_G1S_MASK 0x1 57 #define CTLR_ARE_S_MASK 0x1 58 #define CTLR_ARE_NS_MASK 0x1 59 #define CTLR_DS_MASK 0x1 60 #define CTLR_E1NWF_MASK 0x1 61 #define GICD_CTLR_RWP_MASK 0x1 62 63 #define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) 64 #define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) 65 #define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) 66 #define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) 67 #define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) 68 #define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) 69 #define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) 70 71 /* GICD_IROUTER shifts and masks */ 72 #define IROUTER_SHIFT 0 73 #define IROUTER_IRM_SHIFT 31 74 #define IROUTER_IRM_MASK 0x1 75 76 #define GICV3_IRM_PE 0 77 #define GICV3_IRM_ANY 1 78 79 #define NUM_OF_DIST_REGS 30 80 81 /******************************************************************************* 82 * GICv3 Re-distributor interface registers & constants 83 ******************************************************************************/ 84 #define GICR_PCPUBASE_SHIFT 0x11 85 #define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ 86 #define GICR_CTLR 0x0 87 #define GICR_TYPER 0x08 88 #define GICR_WAKER 0x14 89 #define GICR_PROPBASER 0x70 90 #define GICR_PENDBASER 0x78 91 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) 92 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) 93 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) 94 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + 0x200) 95 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + 0x280) 96 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300) 97 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380) 98 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) 99 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) 100 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) 101 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) 102 #define GICR_NSACR (GICR_SGIBASE_OFFSET + 0xe00) 103 104 /* GICR_CTLR bit definitions */ 105 #define GICR_CTLR_UWP_SHIFT 31 106 #define GICR_CTLR_UWP_MASK 0x1 107 #define GICR_CTLR_UWP_BIT (1U << GICR_CTLR_UWP_SHIFT) 108 #define GICR_CTLR_RWP_SHIFT 3 109 #define GICR_CTLR_RWP_MASK 0x1 110 #define GICR_CTLR_RWP_BIT (1U << GICR_CTLR_RWP_SHIFT) 111 #define GICR_CTLR_EN_LPIS_BIT (1U << 0) 112 113 /* GICR_WAKER bit definitions */ 114 #define WAKER_CA_SHIFT 2 115 #define WAKER_PS_SHIFT 1 116 117 #define WAKER_CA_MASK 0x1 118 #define WAKER_PS_MASK 0x1 119 120 #define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) 121 #define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) 122 123 /* GICR_TYPER bit definitions */ 124 #define TYPER_AFF_VAL_SHIFT 32 125 #define TYPER_PROC_NUM_SHIFT 8 126 #define TYPER_LAST_SHIFT 4 127 128 #define TYPER_AFF_VAL_MASK 0xffffffff 129 #define TYPER_PROC_NUM_MASK 0xffff 130 #define TYPER_LAST_MASK 0x1 131 132 #define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) 133 134 #define NUM_OF_REDIST_REGS 30 135 136 /******************************************************************************* 137 * GICv3 CPU interface registers & constants 138 ******************************************************************************/ 139 /* ICC_SRE bit definitions*/ 140 #define ICC_SRE_EN_BIT (1 << 3) 141 #define ICC_SRE_DIB_BIT (1 << 2) 142 #define ICC_SRE_DFB_BIT (1 << 1) 143 #define ICC_SRE_SRE_BIT (1 << 0) 144 145 /* ICC_IGRPEN1_EL3 bit definitions */ 146 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 147 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 148 149 #define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 150 #define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) 151 152 /* ICC_IGRPEN0_EL1 bit definitions */ 153 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 154 #define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) 155 156 /* ICC_HPPIR0_EL1 bit definitions */ 157 #define HPPIR0_EL1_INTID_SHIFT 0 158 #define HPPIR0_EL1_INTID_MASK 0xffffff 159 160 /* ICC_HPPIR1_EL1 bit definitions */ 161 #define HPPIR1_EL1_INTID_SHIFT 0 162 #define HPPIR1_EL1_INTID_MASK 0xffffff 163 164 /* ICC_IAR0_EL1 bit definitions */ 165 #define IAR0_EL1_INTID_SHIFT 0 166 #define IAR0_EL1_INTID_MASK 0xffffff 167 168 /* ICC_IAR1_EL1 bit definitions */ 169 #define IAR1_EL1_INTID_SHIFT 0 170 #define IAR1_EL1_INTID_MASK 0xffffff 171 172 /* ICC SGI macros */ 173 #define SGIR_TGT_MASK 0xffff 174 #define SGIR_AFF1_SHIFT 16 175 #define SGIR_INTID_SHIFT 24 176 #define SGIR_INTID_MASK 0xf 177 #define SGIR_AFF2_SHIFT 32 178 #define SGIR_IRM_SHIFT 40 179 #define SGIR_IRM_MASK 0x1 180 #define SGIR_AFF3_SHIFT 48 181 #define SGIR_AFF_MASK 0xf 182 183 #define SGIR_IRM_TO_AFF 0 184 185 #define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \ 186 ((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ 187 (((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ 188 (((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ 189 (((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ 190 (((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ 191 ((tgt) & SGIR_TGT_MASK)) 192 193 /***************************************************************************** 194 * GICv3 ITS registers and constants 195 *****************************************************************************/ 196 197 #define GITS_CTLR 0x0 198 #define GITS_IIDR 0x4 199 #define GITS_TYPER 0x8 200 #define GITS_CBASER 0x80 201 #define GITS_CWRITER 0x88 202 #define GITS_CREADR 0x90 203 #define GITS_BASER 0x100 204 205 /* GITS_CTLR bit definitions */ 206 #define GITS_CTLR_ENABLED_BIT 1 207 #define GITS_CTLR_QUIESCENT_SHIFT 31 208 #define GITS_CTLR_QUIESCENT_BIT (1U << GITS_CTLR_QUIESCENT_SHIFT) 209 210 #ifndef __ASSEMBLY__ 211 212 #include <gic_common.h> 213 #include <interrupt_props.h> 214 #include <stdint.h> 215 #include <types.h> 216 #include <utils_def.h> 217 218 #define gicv3_is_intr_id_special_identifier(id) \ 219 (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) 220 221 /******************************************************************************* 222 * Helper GICv3 macros for SEL1 223 ******************************************************************************/ 224 #define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ 225 IAR1_EL1_INTID_MASK 226 #define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ 227 HPPIR1_EL1_INTID_MASK 228 #define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) 229 230 231 /******************************************************************************* 232 * Helper GICv3 macros for EL3 233 ******************************************************************************/ 234 #define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ 235 IAR0_EL1_INTID_MASK 236 #define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) 237 238 /* 239 * This macro returns the total number of GICD registers corresponding to 240 * the name. 241 */ 242 #define GICD_NUM_REGS(reg_name) \ 243 DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT)) 244 245 #define GICR_NUM_REGS(reg_name) \ 246 DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT)) 247 248 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 249 #define INT_ID_MASK 0xffffff 250 251 /******************************************************************************* 252 * This structure describes some of the implementation defined attributes of the 253 * GICv3 IP. It is used by the platform port to specify these attributes in order 254 * to initialise the GICV3 driver. The attributes are described below. 255 * 256 * The 'gicd_base' field contains the base address of the Distributor interface 257 * programmer's view. 258 * 259 * The 'gicr_base' field contains the base address of the Re-distributor 260 * interface programmer's view. 261 * 262 * The 'g0_interrupt_array' field is a pointer to an array in which each entry 263 * corresponds to an ID of a Group 0 interrupt. This field is ignored when 264 * 'interrupt_props' field is used. This field is deprecated. 265 * 266 * The 'g0_interrupt_num' field contains the number of entries in the 267 * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is 268 * used. This field is deprecated. 269 * 270 * The 'g1s_interrupt_array' field is a pointer to an array in which each entry 271 * corresponds to an ID of a Group 1 interrupt. This field is ignored when 272 * 'interrupt_props' field is used. This field is deprecated. 273 * 274 * The 'g1s_interrupt_num' field contains the number of entries in the 275 * 'g1s_interrupt_array'. This field must be 0 if 'interrupt_props' field is 276 * used. This field is ignored when 'interrupt_props' field is used. This field 277 * is deprecated. 278 * 279 * The 'interrupt_props' field is a pointer to an array that enumerates secure 280 * interrupts and their properties. If this field is not NULL, both 281 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 282 * 283 * The 'interrupt_props_num' field contains the number of entries in the 284 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num' 285 * and 'g1s_interrupt_num' are ignored. 286 * 287 * The 'rdistif_num' field contains the number of Redistributor interfaces the 288 * GIC implements. This is equal to the number of CPUs or CPU interfaces 289 * instantiated in the GIC. 290 * 291 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for 292 * storing the base address of the Redistributor interface frame of each CPU in 293 * the system. The size of the array = 'rdistif_num'. The base addresses are 294 * detected during driver initialisation. 295 * 296 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the 297 * driver will use to convert an MPIDR value to a linear core index. This index 298 * will be used for accessing the 'rdistif_base_addrs' array. This is an 299 * optional field. A GICv3 implementation maps each MPIDR to a linear core index 300 * as well. This mapping can be found by reading the "Affinity Value" and 301 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 302 * "Processor Numbers" are suitable to index into an array to access core 303 * specific information. If this not the case, the platform port must provide a 304 * hash function. Otherwise, the "Processor Number" field will be used to access 305 * the array elements. 306 ******************************************************************************/ 307 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 308 309 typedef struct gicv3_driver_data { 310 uintptr_t gicd_base; 311 uintptr_t gicr_base; 312 #if !ERROR_DEPRECATED 313 unsigned int g0_interrupt_num __deprecated; 314 unsigned int g1s_interrupt_num __deprecated; 315 const unsigned int *g0_interrupt_array __deprecated; 316 const unsigned int *g1s_interrupt_array __deprecated; 317 #endif 318 const interrupt_prop_t *interrupt_props; 319 unsigned int interrupt_props_num; 320 unsigned int rdistif_num; 321 uintptr_t *rdistif_base_addrs; 322 mpidr_hash_fn mpidr_to_core_pos; 323 } gicv3_driver_data_t; 324 325 typedef struct gicv3_redist_ctx { 326 /* 64 bits registers */ 327 uint64_t gicr_propbaser; 328 uint64_t gicr_pendbaser; 329 330 /* 32 bits registers */ 331 uint32_t gicr_ctlr; 332 uint32_t gicr_igroupr0; 333 uint32_t gicr_isenabler0; 334 uint32_t gicr_ispendr0; 335 uint32_t gicr_isactiver0; 336 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; 337 uint32_t gicr_icfgr0; 338 uint32_t gicr_icfgr1; 339 uint32_t gicr_igrpmodr0; 340 uint32_t gicr_nsacr; 341 } gicv3_redist_ctx_t; 342 343 typedef struct gicv3_dist_ctx { 344 /* 64 bits registers */ 345 uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM]; 346 347 /* 32 bits registers */ 348 uint32_t gicd_ctlr; 349 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)]; 350 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)]; 351 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)]; 352 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)]; 353 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)]; 354 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)]; 355 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)]; 356 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)]; 357 } gicv3_dist_ctx_t; 358 359 typedef struct gicv3_its_ctx { 360 /* 64 bits registers */ 361 uint64_t gits_cbaser; 362 uint64_t gits_cwriter; 363 uint64_t gits_baser[8]; 364 365 /* 32 bits registers */ 366 uint32_t gits_ctlr; 367 } gicv3_its_ctx_t; 368 369 /******************************************************************************* 370 * GICv3 EL3 driver API 371 ******************************************************************************/ 372 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 373 void gicv3_distif_init(void); 374 void gicv3_rdistif_init(unsigned int proc_num); 375 void gicv3_rdistif_on(unsigned int proc_num); 376 void gicv3_rdistif_off(unsigned int proc_num); 377 void gicv3_cpuif_enable(unsigned int proc_num); 378 void gicv3_cpuif_disable(unsigned int proc_num); 379 unsigned int gicv3_get_pending_interrupt_type(void); 380 unsigned int gicv3_get_pending_interrupt_id(void); 381 unsigned int gicv3_get_interrupt_type(unsigned int id, 382 unsigned int proc_num); 383 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); 384 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); 385 /* 386 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if 387 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no 388 * implementation-defined sequence is needed at these steps, an empty function 389 * can be provided. 390 */ 391 void gicv3_distif_post_restore(unsigned int proc_num); 392 void gicv3_distif_pre_save(unsigned int proc_num); 393 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx); 394 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx); 395 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx); 396 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx); 397 398 unsigned int gicv3_get_running_priority(void); 399 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num); 400 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); 401 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); 402 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 403 unsigned int priority); 404 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 405 unsigned int type); 406 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target); 407 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, 408 u_register_t mpidr); 409 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); 410 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); 411 unsigned int gicv3_set_pmr(unsigned int mask); 412 413 #endif /* __ASSEMBLY__ */ 414 #endif /* __GICV3_H__ */ 415