1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl31.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <cortex_a53.h> 14 #include <cortex_a57.h> 15 #include <debug.h> 16 #include <denver.h> 17 #include <errno.h> 18 #include <memctrl.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <stddef.h> 23 #include <string.h> 24 #include <tegra_def.h> 25 #include <tegra_private.h> 26 #include <utils_def.h> 27 28 /* length of Trusty's input parameters (in bytes) */ 29 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 30 31 extern void zeromem16(void *mem, unsigned int length); 32 33 /******************************************************************************* 34 * Declarations of linker defined symbols which will help us find the layout 35 * of trusted SRAM 36 ******************************************************************************/ 37 38 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 39 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 40 IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); 41 IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); 42 IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); 43 IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); 44 45 extern uint64_t tegra_bl31_phys_base; 46 extern uint64_t tegra_console_base; 47 48 49 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 50 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 51 .tzdram_size = (uint64_t)TZDRAM_SIZE 52 }; 53 static unsigned long bl32_mem_size; 54 static unsigned long bl32_boot_params; 55 56 /******************************************************************************* 57 * This variable holds the non-secure image entry address 58 ******************************************************************************/ 59 extern uint64_t ns_image_entrypoint; 60 61 /******************************************************************************* 62 * The following platform setup functions are weakly defined. They 63 * provide typical implementations that will be overridden by a SoC. 64 ******************************************************************************/ 65 #pragma weak plat_early_platform_setup 66 #pragma weak plat_get_bl31_params 67 #pragma weak plat_get_bl31_plat_params 68 69 void plat_early_platform_setup(void) 70 { 71 ; /* do nothing */ 72 } 73 74 bl31_params_t *plat_get_bl31_params(void) 75 { 76 return NULL; 77 } 78 79 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 80 { 81 return NULL; 82 } 83 84 /******************************************************************************* 85 * Return a pointer to the 'entry_point_info' structure of the next image for 86 * security state specified. BL33 corresponds to the non-secure image type 87 * while BL32 corresponds to the secure image type. 88 ******************************************************************************/ 89 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 90 { 91 if (type == NON_SECURE) 92 return &bl33_image_ep_info; 93 94 /* return BL32 entry point info if it is valid */ 95 if (type == SECURE && bl32_image_ep_info.pc) 96 return &bl32_image_ep_info; 97 98 return NULL; 99 } 100 101 /******************************************************************************* 102 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 103 * passes this platform specific information. 104 ******************************************************************************/ 105 plat_params_from_bl2_t *bl31_get_plat_params(void) 106 { 107 return &plat_bl31_params_from_bl2; 108 } 109 110 /******************************************************************************* 111 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 112 * info. 113 ******************************************************************************/ 114 void bl31_early_platform_setup(bl31_params_t *from_bl2, 115 void *plat_params_from_bl2) 116 { 117 plat_params_from_bl2_t *plat_params = 118 (plat_params_from_bl2_t *)plat_params_from_bl2; 119 #if LOG_LEVEL >= LOG_LEVEL_INFO 120 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 121 #endif 122 image_info_t bl32_img_info = { {0} }; 123 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 124 125 /* 126 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 127 * there's no argument to relay from a previous bootloader. Platforms 128 * might use custom ways to get arguments, so provide handlers which 129 * they can override. 130 */ 131 if (from_bl2 == NULL) 132 from_bl2 = plat_get_bl31_params(); 133 if (plat_params == NULL) 134 plat_params = plat_get_bl31_plat_params(); 135 136 /* 137 * Copy BL3-3, BL3-2 entry point information. 138 * They are stored in Secure RAM, in BL2's address space. 139 */ 140 assert(from_bl2); 141 assert(from_bl2->bl33_ep_info); 142 bl33_image_ep_info = *from_bl2->bl33_ep_info; 143 144 if (from_bl2->bl32_ep_info) { 145 bl32_image_ep_info = *from_bl2->bl32_ep_info; 146 bl32_mem_size = from_bl2->bl32_ep_info->args.arg0; 147 bl32_boot_params = from_bl2->bl32_ep_info->args.arg2; 148 } 149 150 /* 151 * Parse platform specific parameters - TZDRAM aperture base and size 152 */ 153 assert(plat_params); 154 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 155 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 156 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 157 158 /* 159 * It is very important that we run either from TZDRAM or TZSRAM base. 160 * Add an explicit check here. 161 */ 162 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 163 (TEGRA_TZRAM_BASE != BL31_BASE)) 164 panic(); 165 166 /* 167 * Get the base address of the UART controller to be used for the 168 * console 169 */ 170 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 171 172 if (tegra_console_base != (uint64_t)0) { 173 /* 174 * Configure the UART port to be used as the console 175 */ 176 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 177 TEGRA_CONSOLE_BAUDRATE); 178 } 179 180 /* 181 * Initialize delay timer 182 */ 183 tegra_delay_timer_init(); 184 185 /* 186 * Do initial security configuration to allow DRAM/device access. 187 */ 188 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 189 plat_bl31_params_from_bl2.tzdram_size); 190 191 /* 192 * The previous bootloader might not have placed the BL32 image 193 * inside the TZDRAM. We check the BL32 image info to find out 194 * the base/PC values and relocate the image if necessary. 195 */ 196 if (from_bl2->bl32_image_info) { 197 198 bl32_img_info = *from_bl2->bl32_image_info; 199 200 /* Relocate BL32 if it resides outside of the TZDRAM */ 201 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 202 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 203 plat_bl31_params_from_bl2.tzdram_size; 204 bl32_start = bl32_img_info.image_base; 205 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 206 207 assert(tzdram_end > tzdram_start); 208 assert(bl32_end > bl32_start); 209 assert(bl32_image_ep_info.pc > tzdram_start); 210 assert(bl32_image_ep_info.pc < tzdram_end); 211 212 /* relocate BL32 */ 213 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 214 215 INFO("Relocate BL32 to TZDRAM\n"); 216 217 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 218 (void *)(uintptr_t)bl32_start, 219 bl32_img_info.image_size); 220 221 /* clean up non-secure intermediate buffer */ 222 zeromem16((void *)(uintptr_t)bl32_start, 223 bl32_img_info.image_size); 224 } 225 } 226 227 /* Early platform setup for Tegra SoCs */ 228 plat_early_platform_setup(); 229 230 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 231 "Denver" : "ARM", read_mpidr()); 232 } 233 234 #ifdef SPD_trusty 235 void plat_trusty_set_boot_args(aapcs64_params_t *args) 236 { 237 args->arg0 = bl32_mem_size; 238 args->arg1 = bl32_boot_params; 239 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 240 } 241 #endif 242 243 /******************************************************************************* 244 * Initialize the gic, configure the SCR. 245 ******************************************************************************/ 246 void bl31_platform_setup(void) 247 { 248 uint32_t tmp_reg; 249 250 /* Initialize the gic cpu and distributor interfaces */ 251 plat_gic_setup(); 252 253 /* 254 * Setup secondary CPU POR infrastructure. 255 */ 256 plat_secondary_setup(); 257 258 /* 259 * Initial Memory Controller configuration. 260 */ 261 tegra_memctrl_setup(); 262 263 /* 264 * Set up the TZRAM memory aperture to allow only secure world 265 * access 266 */ 267 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 268 269 /* Set the next EL to be AArch64 */ 270 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 271 write_scr(tmp_reg); 272 273 INFO("BL3-1: Tegra platform setup complete\n"); 274 } 275 276 /******************************************************************************* 277 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 278 ******************************************************************************/ 279 void bl31_plat_runtime_setup(void) 280 { 281 /* 282 * During boot, USB3 and flash media (SDMMC/SATA) devices need 283 * access to IRAM. Because these clients connect to the MC and 284 * do not have a direct path to the IRAM, the MC implements AHB 285 * redirection during boot to allow path to IRAM. In this mode 286 * accesses to a programmed memory address aperture are directed 287 * to the AHB bus, allowing access to the IRAM. This mode must be 288 * disabled before we jump to the non-secure world. 289 */ 290 tegra_memctrl_disable_ahb_redirection(); 291 } 292 293 /******************************************************************************* 294 * Perform the very early platform specific architectural setup here. At the 295 * moment this only intializes the mmu in a quick and dirty way. 296 ******************************************************************************/ 297 void bl31_plat_arch_setup(void) 298 { 299 unsigned long rw_start = BL31_RW_START; 300 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 301 unsigned long rodata_start = BL31_RODATA_BASE; 302 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 303 unsigned long code_base = TEXT_START; 304 unsigned long code_size = TEXT_END - TEXT_START; 305 const mmap_region_t *plat_mmio_map = NULL; 306 #if USE_COHERENT_MEM 307 unsigned long coh_start, coh_size; 308 #endif 309 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 310 311 /* add memory regions */ 312 mmap_add_region(rw_start, rw_start, 313 rw_size, 314 MT_MEMORY | MT_RW | MT_SECURE); 315 mmap_add_region(rodata_start, rodata_start, 316 rodata_size, 317 MT_RO_DATA | MT_SECURE); 318 mmap_add_region(code_base, code_base, 319 code_size, 320 MT_CODE | MT_SECURE); 321 322 /* map TZDRAM used by BL31 as coherent memory */ 323 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 324 mmap_add_region(params_from_bl2->tzdram_base, 325 params_from_bl2->tzdram_base, 326 BL31_SIZE, 327 MT_DEVICE | MT_RW | MT_SECURE); 328 } 329 330 #if USE_COHERENT_MEM 331 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 332 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 333 334 mmap_add_region(coh_start, coh_start, 335 coh_size, 336 MT_DEVICE | MT_RW | MT_SECURE); 337 #endif 338 339 /* map on-chip free running uS timer */ 340 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 341 page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 342 (uint64_t)TEGRA_TMRUS_SIZE, 343 MT_DEVICE | MT_RO | MT_SECURE); 344 345 /* add MMIO space */ 346 plat_mmio_map = plat_get_mmio_map(); 347 if (plat_mmio_map) 348 mmap_add(plat_mmio_map); 349 else 350 WARN("MMIO map not available\n"); 351 352 /* set up translation tables */ 353 init_xlat_tables(); 354 355 /* enable the MMU */ 356 enable_mmu_el3(0); 357 358 INFO("BL3-1: Tegra: MMU enabled\n"); 359 } 360 361 /******************************************************************************* 362 * Check if the given NS DRAM range is valid 363 ******************************************************************************/ 364 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 365 { 366 uint64_t end = base + size_in_bytes; 367 368 /* 369 * Check if the NS DRAM address is valid 370 */ 371 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) { 372 ERROR("NS address is out-of-bounds!\n"); 373 return -EFAULT; 374 } 375 376 /* 377 * TZDRAM aperture contains the BL31 and BL32 images, so we need 378 * to check if the NS DRAM range overlaps the TZDRAM aperture. 379 */ 380 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 381 ERROR("NS address overlaps TZDRAM!\n"); 382 return -ENOTSUP; 383 } 384 385 /* valid NS address */ 386 return 0; 387 } 388