1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <console.h> 9 #include <debug.h> 10 #include <mmio.h> 11 #include <plat_arm.h> 12 #include <platform.h> 13 #include <platform_def.h> 14 #include <platform_sp_min.h> 15 16 #define BL32_END (uintptr_t)(&__BL32_END__) 17 18 static entry_point_info_t bl33_image_ep_info; 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak sp_min_platform_setup 22 #pragma weak sp_min_plat_arch_setup 23 #pragma weak plat_arm_sp_min_early_platform_setup 24 25 /* 26 * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 27 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 28 */ 29 CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 30 31 /******************************************************************************* 32 * Return a pointer to the 'entry_point_info' structure of the next image for the 33 * security state specified. BL33 corresponds to the non-secure image type 34 * while BL32 corresponds to the secure image type. A NULL pointer is returned 35 * if the image does not exist. 36 ******************************************************************************/ 37 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 38 { 39 entry_point_info_t *next_image_info; 40 41 next_image_info = &bl33_image_ep_info; 42 43 /* 44 * None of the images on the ARM development platforms can have 0x0 45 * as the entrypoint 46 */ 47 if (next_image_info->pc) 48 return next_image_info; 49 else 50 return NULL; 51 } 52 53 /******************************************************************************* 54 * Utility function to perform early platform setup. 55 ******************************************************************************/ 56 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 57 uintptr_t hw_config, void *plat_params_from_bl2) 58 { 59 /* Initialize the console to provide early debug support */ 60 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, 61 ARM_CONSOLE_BAUDRATE); 62 63 #if RESET_TO_SP_MIN 64 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 65 assert(from_bl2 == NULL); 66 assert(plat_params_from_bl2 == NULL); 67 68 /* Populate entry point information for BL33 */ 69 SET_PARAM_HEAD(&bl33_image_ep_info, 70 PARAM_EP, 71 VERSION_1, 72 0); 73 /* 74 * Tell SP_MIN where the non-trusted software image 75 * is located and the entry state information 76 */ 77 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 78 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 79 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 80 81 #else /* RESET_TO_SP_MIN */ 82 83 /* 84 * Check params passed from BL2 should not be NULL, 85 */ 86 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 87 assert(params_from_bl2 != NULL); 88 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 89 assert(params_from_bl2->h.version >= VERSION_2); 90 91 bl_params_node_t *bl_params = params_from_bl2->head; 92 93 /* 94 * Copy BL33 entry point information. 95 * They are stored in Secure RAM, in BL2's address space. 96 */ 97 while (bl_params) { 98 if (bl_params->image_id == BL33_IMAGE_ID) { 99 bl33_image_ep_info = *bl_params->ep_info; 100 break; 101 } 102 103 bl_params = bl_params->next_params_info; 104 } 105 106 if (bl33_image_ep_info.pc == 0) 107 panic(); 108 109 #endif /* RESET_TO_SP_MIN */ 110 111 } 112 113 /******************************************************************************* 114 * Default implementation for sp_min_platform_setup2() for ARM platforms 115 ******************************************************************************/ 116 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 117 u_register_t arg2, u_register_t arg3) 118 { 119 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 120 121 /* 122 * Initialize Interconnect for this cluster during cold boot. 123 * No need for locks as no other CPU is active. 124 */ 125 plat_arm_interconnect_init(); 126 127 /* 128 * Enable Interconnect coherency for the primary CPU's cluster. 129 * Earlier bootloader stages might already do this (e.g. Trusted 130 * Firmware's BL1 does it) but we can't assume so. There is no harm in 131 * executing this code twice anyway. 132 * Platform specific PSCI code will enable coherency for other 133 * clusters. 134 */ 135 plat_arm_interconnect_enter_coherency(); 136 } 137 138 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 139 u_register_t arg2, u_register_t arg3) 140 { 141 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 142 } 143 144 /******************************************************************************* 145 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 146 * Common to ARM standard platforms. 147 ******************************************************************************/ 148 void arm_sp_min_plat_runtime_setup(void) 149 { 150 /* Initialize the runtime console */ 151 console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE, 152 PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE); 153 } 154 155 /******************************************************************************* 156 * Perform platform specific setup for SP_MIN 157 ******************************************************************************/ 158 void sp_min_platform_setup(void) 159 { 160 /* Initialize the GIC driver, cpu and distributor interfaces */ 161 plat_arm_gic_driver_init(); 162 plat_arm_gic_init(); 163 164 /* 165 * Do initial security configuration to allow DRAM/device access 166 * (if earlier BL has not already done so). 167 */ 168 #if RESET_TO_SP_MIN 169 plat_arm_security_setup(); 170 171 #if defined(PLAT_ARM_MEM_PROT_ADDR) 172 arm_nor_psci_do_dyn_mem_protect(); 173 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 174 175 #endif 176 177 /* Enable and initialize the System level generic timer */ 178 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 179 CNTCR_FCREQ(0) | CNTCR_EN); 180 181 /* Allow access to the System counter timer module */ 182 arm_configure_sys_timer(); 183 184 /* Initialize power controller before setting up topology */ 185 plat_arm_pwrc_setup(); 186 } 187 188 void sp_min_plat_runtime_setup(void) 189 { 190 arm_sp_min_plat_runtime_setup(); 191 } 192 193 /******************************************************************************* 194 * Perform the very early platform specific architectural setup here. At the 195 * moment this only initializes the MMU 196 ******************************************************************************/ 197 void sp_min_plat_arch_setup(void) 198 { 199 200 arm_setup_page_tables(BL32_BASE, 201 (BL32_END - BL32_BASE), 202 BL_CODE_BASE, 203 BL_CODE_END, 204 BL_RO_DATA_BASE, 205 BL_RO_DATA_END 206 #if USE_COHERENT_MEM 207 , BL_COHERENT_RAM_BASE, 208 BL_COHERENT_RAM_END 209 #endif 210 ); 211 212 enable_mmu_secure(0); 213 } 214